KR930002127B1 - All channel pattern generator - Google Patents

Abstract

The generator generates all channel (CH2-CH83) pattern to help concerned engineers servicing television nsets. It includes a keyboard for selecting a channel and pattern, a one-chip microprocessor (5) for controlling the circuit, an electronic tuner (7) for generating a certain channel frequency corresponding to the control signal from the microprocessor (5), a channel selecting & function controlling section for selecting & generating appropriate channel frequency, a ROM1 (17) for generating the block data corresponding to the control of the microprocessor (5), and an outputter buffer (21) for applying the pattern data from a pattern data composer (20) to an RF modulator (10).

Description

All Channel Pattern Generator

1 is a block diagram of a channel selection and function control unit of a pattern generator according to the present invention.

2 is a block diagram showing a pattern generator of the pattern generator according to the present invention.

3 is a block diagram showing a one chip microcomputer and an electronic tuner.

4A is a block diagram illustrating the operation of the RF amplification / divider according to the present invention.

4B is a circuit diagram showing a circuit for RF amplification and divider according to the present invention.

5 is a flowchart showing processing operations in ROM1.

6 is a flowchart showing processing operations in ROM2.

7 is a flowchart showing processing operations in a one-chip microcomputer.

* Explanation of symbols for main parts of the drawings

1: clock oscillator 2: keyboard

3: display 4: input / output port

5: one chip microcomputer 6: buffer

7: Electronic tuner 8: Relay

9: RF amplification / divider 10: RF modulator

11: connector 12: crystal

13: 1 / N divider 14: oscillator

15: horizontal and vertical synchronous signal synthesizer 16: signal selector

17: ROM1 18: ROM2

19: luminance signal generator 20: pattern data mixer

21: output buffer

[Industrial use]

The present invention relates to an all-channel pattern generator that enables repair and adjustment by generating a pattern and transmitting it to the TV even when it is not a TV broadcast time during repair and adjustment of the TV of the present invention.

[Traditional Technology and Problems]

Conventionally used TV pattern generators are composed of two channels, and one of the equipments for repairing and adjusting the TV has been insufficient. In addition, although the simple pattern generator is composed of multi-channels, the frequency accuracy is low and there is a problem in stability, which is insufficient for practical use.

[Purpose of invention]

The present invention has been invented in view of the above points, and since the signals required for the repair and adjustment of TVs are used in a wide range of broadcasting channels according to each region (CH2 to CH83), it is essential for related engineers and A / S engineers. Its purpose is to provide an All Channel Pattern Generator.

[Configuration of Invention]

In order to achieve the above object, the present invention provides a clock oscillator (1) for generating a clock signal to operate the system and outputting it to the input / output shaft (4) and the one-chip microcomputer (5), and in the form of a channel. A keyboard (2) for selecting a channel, a display (3) for selecting channel selection and patterns, a signal input from the clock oscillator (1) and the keyboard (2), and the display (3) and a one-chip microcomputer (5). Input / output port (4) for outputting a signal to the device, a one-chip microcomputer (5) for controlling all functions of the system, and a buffer for outputting control signals from the one-chip microcomputer (5) to each control terminal of the connector (11). (6), an electronic tuner (7) which oscillates and outputs a corresponding channel frequency by the control signal from the one-chip microcomputer (5), and oscillates a frequency corresponding to channels 2 to 6 by the electronic tuner (7). When is this week A relay 8 for switching the terminal of the switch SW so that the wave signal is output to the RF modulator 10 through the RF amplifier / divider 9, and an RF that amplifies and divides the frequencies corresponding to the channels 2 to 6. A channel tuning and function control unit comprising an amplifying / divider 9 and an RF modulator 10 for RF modulating and outputting the frequency signal from the electronic tuner 7; 1 / N frequency divider 13 which receives the crystal 12 to generate, and the fundamental frequency generated from this crystal 12, and divides the color synchronous signal and the horizontal and vertical synchronous signals to generate the 1 / N divider. An oscillator 14 which receives a signal from the period 13 and outputs a clock signal for vertical frequency to the horizontal and vertical synchronizing signal synthesizer 15, and a horizontal synchronizing signal and an oscillator input from the 1 / N divider 13; Signal selection by synthesizing the vertical synchronous signal input from 14) The horizontal / vertical synchronous signal synthesizer 15 to be output to the device 16, the signal selector 16 to select a frequency suitable for each pattern when it is color or mono, and output it to the output buffer 21, and each pattern A data block for distinguishing is embedded in the program, and ROM1117 outputs corresponding data according to a command inputted through the control terminal of the connector 11 from the one-chip microcomputer 5, and data from the ROM1 (17). ROM2 (18) receiving the input and outputting detailed data constituting the character and color to the pattern data mixer 20, and generates and outputs a luminance signal suitable for the pattern to be displayed in bright order by receiving data from the ROM1 (17) Pattern data for receiving the data input from the luminance signal generator 19 and the ROM2 18 and the signal input from the signal selector 16 to create and output predetermined pattern data selected by the control terminal. The mixer 20, a video input terminal OUT1 which can be used when necessary, is installed, and a terminal OUT2 for outputting a signal to the RF modulator 10 is installed, and the pattern data input from the pattern data mixer 20 is provided. It is configured to include a pattern generator consisting of an output buffer 21 for output to the RF modulator (10).

[Action]

The present invention configured as described above can oscillate the frequencies of all the channels of VHF CH2 to CH6, VHF CH7 to CH13, and UHF CH14 to CH83, and thus there is no limit to the channels that can be used. You can send the desired pattern to.

EXAMPLE

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In FIG. 1, the clock oscillator 1 generates a clock signal to operate the system and outputs the clock signal to the input / output port 4 and the one chip microcomputer 5. Next, when a predetermined signal is input to the input / output port 4 by the keyboard 2 configured in the form of a matrix and selects a channel selection and a pattern, the input / output port 4 outputs a signal to the display 3 so that The selection state of channel selection and pattern is displayed on this display 3, and at the same time, a signal is output to the one-chip microcomputer 5 as well.

The one-chip microcomputer 5 is an IC that controls all functions of the system. When a predetermined signal is input from the input / output port 4, the one-chip microcomputer 5 outputs a signal to the buffer 6, and the keyboard 6 The generation signal of the predetermined pattern selected in Fig. 2 is outputted to the pattern generation unit shown in FIG. 2 through each control terminal of the connector l1. In addition, data necessary for oscillation of the electronic tuner 7 is stored, and a signal is output to the pattern generator, and at the same time, data necessary for oscillation is output to the electronic tuner 7.

In this case, if one of VHF 2 to 6CH is selected and used, the one-chip microcomputer 5 outputs a drive signal to the relay 8 to change the terminal b of the switch SW to the terminal c. After that, the output from the electronic tuner 7 is amplified and divided by the RF amplifier and divider 9, and then modulated by the RF modulator 10 to be output to the RF output terminal. On the other hand, the relay 8 is not driven when a channel other than the VHF channels 2-6 is selected and used, so that the output from the electronic tuner 7 is directly output to the RF output terminal through the RF modulator 10. do. When the VHF 2 to 6 channels are selected and used, the oscillation in the tuner 7 and the operation relationship of the RF amplification / divider 9 will be described in detail with reference to FIG.

Next, FIG. 2 shows a block diagram of a pattern generator that generates a pattern required for use. Here, the connector 11 is the same as that of FIG. 1, and is connected to send data input from the one-chip microcomputer 5 shown in FIG. 1 to the signal selector 16 and ROM1 17 of FIG. The operation of FIG. 2 is as follows. The crystal 12 is an oscillator that generates the required frequency in the minimum unit necessary for pattern formation, and outputs a frequency signal OSC as a 1 / N divider 13. Next, the 1 / N divider 13 receives the fundamental frequency generated from the crystal 12 and divides and generates the required frequency signals, that is, color synchronization signals and horizontal and vertical synchronization signals. The oscillator 14 receives the signal input from the 1 / N divider 13 and outputs a clock signal for vertical frequency to the horizontal and vertical synchronizing signal synthesizer 15. The horizontal and vertical synchronizing signal synthesizer 15 The horizontal synchronous signal input from the 1 / N divider 13 and the vertical synchronous signal input from the oscillator 14 are synthesized and output to the signal selector 16. The signal selector 16 receives a color synchronization signal from the 1 / N divider 13, and selects a frequency corresponding to each pattern when it is color or mono, through a control terminal, and outputs the output buffer ( 21)

On the other hand, ROM1 (17) has a data block for dividing each pattern into a program, and the corresponding data is read from the one-chip microcomputer (5) of FIG. 1 in accordance with a command input through the control terminal of the connector (11). Output to (18). At the same time, the luminance signal generator 19 also outputs the luminance signal data. The luminance signal generator 19 receives data from the ROM1 (7), generates luminance corresponding to a pattern to be displayed in bright order, and outputs the luminance to the output buffer 21. The ROM2 18 receives data from the ROM1 17 and outputs detailed data constituting the detailed character and color of the data block to the pattern data mixer 20. The pattern data mixer 20 receives data input from the ROM2 18 and signals (color signals, horizontal and vertical synchronization signals) input from the signal selector 16, and receives predetermined pattern data selected by the control terminal. And output to the output buffer 21. The output buffer 21 is provided with a video input terminal OUT1 which can be used for a VTR if necessary, and a terminal OUT2 for outputting a signal to the RF modulator 10 of FIG. 1 is provided. The pattern data input from the mixer 20 is transmitted to the TV through the RF modulator 10.

Next, the operation relationship between the one-chip microcomputer 5 and the electronic tuner 7 according to the present invention will be described in detail with reference to FIG. Here, the electronic tuner 7 used is the same as the conventional tuner.

분주한다. 이때, 주파수를 증폭하는 것은 분주 IC에서 받아들일 수 있는 신호레벨로 하기 위해서이다.First, when a channel is selected by the keyboard 2, a signal corresponding to the channel is input to the one chip microcomputer 5 through the input / output port 4, and the one chip microcomputer 5 corresponds to CH2 to CH83. When data is stored and a signal is input from the keyboard 2, the corresponding data signal is outputted to a PLL (Phase Locked Loop) IC built in the tuner 7, and also an enable signal and a clock signal. Output to the PLL IC. The PLL IC embedded in the tuner 7 selects and drives one of three channel frequency oscillators OSC1, OSC2, and OSC3 when a data signal is input from the one-chip microcomputer 5 to generate a corresponding channel frequency. This is amplified by the RF amplifier and outputs an RF carrier. Here, the PLL (Phase Locked Loop) method stabilizes the generated frequency. By controlling the power supply, the correct frequency is automatically maintained during channel frequency oscillation. In addition, the PLL IC has a PLL LOCK terminal, which enables the formation of a PLL. FIG. 4 (a) is a block diagram for explaining the operation of the RF amplifier / divider 9 (CH2 to CH6 generator) according to the present invention. FIG. A circuit diagram showing a circuit. In Fig. 4 (a), since the oscillation of the frequencies corresponding to CH2 to CH6 is impossible in the tuner 7, the one-chip microcomputer makes the tuner 7 oscillate the frequency that is twice the frequency corresponding to CH2 to CH6. It is programmed in (5). Under the control of the one-chip microcomputer 5, the tuner 7 oscillates a frequency which is twice the frequency of one of the predetermined channels (one of CH2 to CH6) and outputs it to the RF amplifier / divider 9. In the wideband amplification and buffer section of the RF amplifier / divider 9, the input frequency is first amplified and then adjusted to a frequency suitable for CH2 to CH6 in the high-speed two-dividing unit.

Busy. At this time, the frequency is amplified in order to make the signal level acceptable to the frequency divider IC.

In FIG. 4 (b), when the double frequency is input through C1 of the RF amplification circuit CT1, the transistor TRl amplifies it and outputs impedance impedance matching by the transistor TR2. The signal is input to the division circuit CT2 through C4. At this time, the bias voltage required for the operation of the frequency divider IC is supplied by a voltage division circuit composed of resistors R7 and R8. The signal input to the dividing IC is divided into two by this dividing IC, and is output to the RF modulator 10 shown in FIG. At this time, the load resistance (R9, R10) of the IC is used to make an accurate division. The divided output is a frequency corresponding to CH2 to CH6.

That is,

Next, the processing operation in the ROM 17 will be described with reference to the flowchart of FIG. First, in step 1, the address is initially set to pattern 1. In the next step 2, the pattern is selected and input from the keyboard 2 by the user. That is, a new address is specified. In step 3, if a new address is specified, the process proceeds to step 4, and if no new address is specified, the process returns to step 2 to enter the input standby state. In step 4, the pattern block corresponding to the newly designated address is set, and in step 5, the pattern data corresponding to the set pattern block is output, and then the processing ends.

Next, the processing operation in the ROM2 18 will be described with reference to the flowchart of FIG. In step 11, the data of pattern 1 is set to an initial value. ROM1 in step 12

The address signal is selected and input from (17). If the address signal is input in step 13, the process proceeds to step 14, otherwise the process returns to step 12 to be in a standby state. In step 14, a character or killer corresponding to the input address is set, and after the character or color data corresponding to the pattern selected in step 15 is output, the processing is terminated.

Finally, the processing operation in the one-chip microcomputer 5 will be described with reference to the flowchart of FIG.

In step 21, channel 3 and pattern 1 are set to initial values, and this state is shown on the display. In the next step 22, when the user selects a desired channel and pattern and inputs it on the keyboard, this keyed state is displayed on the display. In step 23, if key input is made, the process proceeds to step 24; otherwise, the process returns to step 22 to enter the key input standby state. In step 24, data corresponding to the selected channel and pattern are selected, and in step 25, the channel frequency data and the selected pattern data are output, and the processing ends.

[Effects of the Invention]

As described above, according to the present invention, in the case of a domestic broadcasting station using all VHF LOW BAND, VHF HIGH BAND, and UHF 3BAND, it is possible to improve the point that it is not easy to repair and adjust the TV when there is no daytime broadcasting. It can help a lot of A / S engineers to perform their work quickly and accurately.

Claims (2)

A clock oscillator 1 for generating and outputting a clock signal to operate the system, a keyboard 2 configured in a matrix form for selecting channel tuning and patterns, a display 3 for displaying channel selection and selection states of the patterns; An input / output port 4 for receiving signals from the clock oscillator 1 and the keyboard 2 and outputting signals to the display 3 and the one-chip microcomputer 5, and a one-chip microcomputer controlling all functions of the system ( 5) A buffer 6 for outputting a control signal from the one-chip microcomputer 5 to each control terminal of the connector 11, and a corresponding channel frequency by the control signal from the one-chip microcomputer 5; When the electronic tuner 7 oscillates and outputs the frequency corresponding to channels 2 to 6 in the electronic tuner 7, the frequency signal is transmitted to the RF modulator 10 through the RF amplification / divider 9. Output of the switch (SW) A relay 8 for switching the ruler, an RF amplifier / divider 9 for amplifying and dividing the frequencies corresponding to the channels 2 to 6, and an RF modulator for RF-modulating and outputting the frequency signal from the electronic tuner 7 10) Channel tuning and function control unit consisting of: crystal 12 to generate the required frequency in the minimum unit required for the pattern configuration, and the base frequency generated from the crystal 12 receives the color synchronization signal and horizontal ㆍ 1 / N divider 13 which divides and generates a vertical synchronous signal, and receives a signal from the 1 / N divider 13 and outputs a clock signal for vertical frequency to the horizontal and vertical synchronous signal synthesizer 15. A horizontal and vertical synchronous signal synthesizer 15 for synthesizing the horizontal synchronous signal input from the oscillator 14 and the 1 / N divider 13 and the vertical synchronous signal input from the oscillator 14 and outputting the synthesized signal to the signal selector 16. ), Color or mono The signal selector 16 which selects a frequency suitable for the pattern and outputs it to the output buffer 2l, and a data block for distinguishing each pattern are built in the program, and each control of the connector 11 from the one chip microcomputer 5 is performed. ROM1 (17) for outputting corresponding data according to the command input through the terminal, ROM2 (18) for receiving data from the ROM1 (17) and outputting detailed data constituting characters and colors to the pattern data mixer 20 (18). ), A luminance signal generator 19 which receives data from the ROM1 17 and generates and outputs a luminance signal corresponding to a pattern to be displayed in a bright order, from the data and the signal selector 16 inputted from the ROM2 18; The pattern data mixer 20 which receives the input signal and generates and outputs predetermined pattern data selected by the control terminal, and a video input terminal OUTl which can be used when necessary, is installed. A terminal (OUT2) for outputting a signal to the RF modulator 10 is provided to have a pattern generator consisting of an output buffer 21 for outputting the pattern data input from the pattern data mixer 20 to the RF modulator 10 All-channel pattern generator, characterized in that configured. 2. The RF amplifier and divider (9) is coupled to a one-chip microcomputer (5) and an electronic tuner (7), wherein the tuner (7) has two frequencies corresponding to channels 2 to 6. After oscillating the double frequency and amplifying the double frequency in the RF amplifier / divider (9),

An all-channel pattern generator characterized by dividing to obtain an accurate frequency of channels 2 to 6.

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