KR930001882Y1 - Current eliminating circuit for input bias - Google Patents

Abstract

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Description

Input bias current cancellation circuit

1 is a conventional input bias current cancellation circuit diagram.

2 is a bias current cancellation circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

11: bias part 12: differential amplifier

13: bias current detector

Q11, Q12, Q23, Q24: Enfine Transistor

Q13, Q14, Q19, Q20: Short Transistor

Q15-Q18, Q25: PNP Transistor

Q21, Q22: Multicollective NP Transistor

The present invention relates to an input bias current cancellation circuit, and more particularly, to an input bias current cancellation circuit suitable for a precision comparator circuit by removing the bias current more completely.

In the conventional input bias current removing circuit, as shown in FIG. 1, the emitters of the transistors (Q1) and (Q2) of the differential amplifier (1) that receive the input signals (Vin1, (Vin2)) are applied to the base. It is commonly connected to the current source I _E and the P and P of the bias part 4 which receives the power supply voltage Vcc to the emitter through the diodes D1 and D2 through the current source I _B. A differential amplification output (Vout) at the collector of transistors Q3 and Q4 connected to the base of transistor Q9 and cascaded to each collector of transistors Q1 and Q2, Transistors of the differential amplification unit 1 through the current source PNP transistors Q5 and Q6 of the bias current unit 2 receiving the bias through the current source I _B of the bias unit 4, respectively. Q3) and the input signal (Vin1) bias current _{(I B3), (I 1} ) the control and bias before receiving the baeo ground through the current source (I _B) of Section 3, the current source P & P transistor (Q7), (Q8) for controlling a bias current (I _B4), (I ₂₎ of the transistor (Q4) and the input signal (Vin2) of said differential amplifier section (1) through the It is configured to.

When the input signals Vin1 and Vin2 are applied to the bases of the transistors Q1 and Q2 of the differential amplifier 1, the input currents Vin1 and Vin2 are applied according to the input signals Vin1 and Vin2. Are applied to the bases of transistors Q1 and Q2, respectively. However, the transistors Q1 and Q2 of the differential amplifier 1 are referred to as transistors Q3 and Q4 that are cascaded, respectively, and the current flowing through the transistors Q1 and Q3 is I. _It becomes _E / 2, and the electric current which flows through transistors Q2 and Q4 also becomes _IE / 2.

If the base current of transistor Q1 is referred to as I _B1 and the base current of transistor Q3 is referred to as I _B3 , since the transistors Q1 and Q3 have the same size and characteristics, the base currents are the same (I _B1). = I _B3 ), while the input current I _B1 is obtained by subtracting the current I1 through the transistor Q6 of the transistor 2 of the bias current 2 from the base current I _B1 of the transistor Q1. , Iin1 = I _B1 -I1.

Similarly, the input current Iin2 of the transistor Q2 becomes Iin2 = I _B2 -I2. At this time, each of the PNP transistors Q6 and Q5 and Q7 and Q8 of the bias current units 2 and 3 is a current mirror, so that I _B3 = I1 and I _B4 = I2. That is, Iin1 = I _B -I1 = I _B1 -I _B3 -Expression (1), and Iin2 = I _B2 -I2 = I _B2 -I _B4 -Expression (2).

Therefore, since the transistors Q1 and Q3 and Q2 and Q4 are the same size and characteristics, the base current is the same, so that Iin1 is the same. 0, Iin2 The input bias currents Iin1 and Iin2 are removed.

However, the base bias currents I _B3 and I _B4 of the transistors Q3 and Q4 are supplied through the PNP transistors Q5 and Q7, and the PNP transistors Q5 and Q7 are supplied. And each of the control currents (Q5, Q6) and (Q7, Q8) through PNP transistors (Q6) and (Q8), which are current mirrors, respectively, so there is a difference between I _B3 and I1 and I _B4 / β (β is Current gain of PNP transistor).

In view of such a problem, the present invention provides a circuit that accurately detects the bias current supplied to the differential amplifier and improves the accuracy of eliminating the input bias current accordingly. Same as

FIG. 2 is a circuit diagram of an input bias current cancellation circuit according to the present invention. As shown therein, the emitters of transistors Q11 and Q12 to which input signals Iin1 and Iin2 are applied to a base are commonly used as current sources I. _E ), and their collectors are cascaded with Schottky transistors Q13 and Q14, respectively, and the common base of the Schottky transistors Q13 and Q14 is connected via a diode D1 to the transistor Q11. ), (12) and (12) to the emitter of the current source PNP transistor (Q25) connected to the base, and the power supply voltage (Vcc) is applied to the emitter through the resistors (R1) and (R2), respectively. The differential amplification output Vo is applied through each collector of the PNP transistors Q15 and Q16 to which the common bias V _Bias is applied to the base and the collector connection points of the Schottky transistors Q13 and Q14. A common base of the differential amplifier 12 and the PNP transistors Q17 and Q18 forming the current mirror; A common base of the group P & P transistor (Q17) connected to the collector of the current source (I _E1) and Schottky transistor (Q13) of the differential amplifying section 12 to the collector of the P & P transistor (Q18), (Q14) The collector is commonly connected to the bias section 11 for supplying a bias current and to the Schottky transistors Q13 and Q14 base common connection point of the differential amplifier 12, and the emitter is commonly connected. It is connected to the bases of the Schottky transistors Q19 and Q20 having the configuration, and connected to the emitter of the multi-collector PNP transistor Q21, and the one collector thereof is connected to its base, and the multi-collector P is connected. The emitter is connected to the emitter of the N-P transistor Q22, the other collector of the multi-collector P-P transistor Q21 is connected to the base of the multi-collector P-P transistor Q22, and the collector is commonly used for the Schottky. Transistor (Q19), connected in common to the meter on and the emitter is connected to common with the current source (I _E2) connected in common, and wherein the multi-collector to the base of the dual configuration of the transistor (Q23), (Q24) of blood (Q20) The multi-collector of the N-pit transistor Q22 is connected to the bases of the transistors Q11 and Q12 of the differential amplifier 12 to form a current mirror, and the schottky transistor Q13 of the differential amplifier 12 is connected. And a bias current detection unit 13 for sensing the base bias currents of Q14 and Q14 and supplying the base biases of the transistors Q11 and Q12.

Referring to the operation and effects of the present invention configured as described above are as follows.

When the input signals Vin1 and Vin2 are input, the differential amplifier 12 through the transistors Q11 and Q12 of the transistors 12 through the Schottky transistors Q13 and Q14. Output (Vo).

At this time, the bias unit 11 receives the base bias currents of the Schottky transistors Q13 and Q14 through the PN transistor Q18 forming a current mirror with the PN transistor Q17 turned on by the current source I _E1 . The base bias current is applied to the bases of the Schottky transistors Q19 and Q20 of the current sensing unit 13 and the emitters of the multi-collector PNP transistor Q21.

The current flowing through the base of the multi-collector PNP transistor Q22 and the current sources I _E2 through the transistors Q23 and Q24 forms a current mirror with the bias unit 11 and the multi-collector PNP transistor Since a current mirror is formed with Q21 and Q22, the bias currents I1 and I2 applied to the base side of the transistors Q11 and Q12 of the differential amplifier 12 and the Schottky transistor ( The base biases of Q13) and Q14 are equal.

That is, if the collector output current of the PNP transistor Q18 of the bias unit 11 is I _B3 , this current I _B3 is applied to the bases of the Schottky transistors Q13 and Q14 and the bias current detection unit 13 Is applied to the Schottky transistors Q19 and Q20, and this bias current I _B3 is applied to the emitter of the multi-collector PNP transistor Q21 acting as a diode and through the other collector thereof. It is applied to the base of the transistor Q22 and flows evenly through the two collectors of the multi-collector PNP transistor Q22.

Accordingly, the bias currents I1 and I2 applied to the base side of the transistors Q11 and Q12 are equal in magnitude, and the collector currents of the transistors Q11 and Q12 are I _E / 2, respectively. The collector currents of the PNP transistors Q17 and Q18 are current source I _E1 currents of the bias unit 11.

Therefore, if I _E1 = I _E = I _E2 , the base bias currents I _B3 of the Schottky transistors Q13 and Q14 are the base bias currents I _B1 and I of transistors Q11 and Q12. _B2 ) twice.

This is as follows.

The input currents Iin1 and Iin2 are represented by Iin1 = I _B1- I1- (3), Iin2 = I _B2- I2- (4), and I _E1 = I _B3 = I _B1 + I _B2 = I _E- (5) Therefore, I _B3 = I _B1 + I _B2 = (Iin1 + I1) + (Iin2 + I2) = I1 + I2 + Iin2- in the above formulas (3), (4) and (5) However, the currents I1 and I2 that are equally divided and flow through the two collectors of the multi-collector PNP transistor Q22 are the collector currents I _B3 of the PNP transistor Q18, that is, I _B3. = I1 + I2- Equation (7).

In formulas (6) and (7), I _B3 = I _B1 + I _B2 = I ₁ + I ₂ -Equation (8), where Iin1 = 0 and Iin2 = 0.

In this way, the input currents Iin1 and Iin2 are removed by the currents I1 and I2 supplied through the bias current detection unit 13.

Here, the schottky transistors Q13 and Q14 of the differential amplifier 12 prevent their collectors from being saturated according to the characteristics of the schottky transistor, and the schottky transistors Q13 and ( The base of Q14) is commonly connected to the PNP transistor Q25 through the diode D1, and the base of the PNP transistor Q25 is connected to the common emitter of the transistors Q11 and Q12. The base collector voltages of the transistors Q11, Q13, and Q12 and Q14 are made constant, and Schottky transistors Q19, Q20, Q20, and the transistor Q23, for the current mirror configuration of the bias current detector 13, The dual configuration of each of Q24 is to give the same condition as the Schottky transistors Q13, Q14, and transistors Q11, Q12 of the differential amplifier 12.

As such, the present invention provides the bias current detection unit 13 such that the base currents I _B3 = 2I _B1 and (I _B3 = 2I _B2 ) of the transistors Q11 and Q13 and Q12 and Q14 of the differential amplifier 12 are the same. By supplying the current (I1) and (I2) accurately through the through, the difference as much as 2I _B3 / β generated in the conventional PNP-type current mirror Cree and refine the degree. That is, about Since there is a difference in degree, it is possible to improve the blocking of the input currents Iin1 and Iin2 much more accurately than in the conventional circuit.

Claims (2)

In the input bias current cancellation circuit of the differential amplification circuit, a schottky transistor (Q13) (Q13) (Q14) connected to the transistors (Q11) (Q12) and (Q12) and its collector to which the input signals (Vin1) (Vin2) are applied to the base. Through the differential amplifier 12, the PNP transistor Q17 controlled according to the current source I _E1 and the PNP transistor Q18 which is the current mirror, the Schottky transistor of the differential amplifier 12 Q13) and (Q14) the bias unit 11 which supplies the base bias current in common, and the Schottky transistors Q13 and (Q14) the base bias current is detected and the current I1 equally divided by the current mirror, And a bias current detection unit 13 for supplying (I2) to the transistors Q11 and Q12 of the differential amplifier 12 to remove the input currents Iin1 and Iin2. Current elimination circuit. The base and multi-collector PNP transistors Q21 according to claim 1, wherein the base connection points of the Schottky transistors Q13 and Q14 are configured as a common collector and a common emitter. To the emitter of < RTI ID = 0.0 > and < / RTI > After the collector is commonly connected to the common emitters of the kit transistors Q19 and Q20, the emitter is connected to the base of the transistors Q23 and Q24 which are commonly connected to the current source I _E2 , and the multi-collector And a bias current detector (13) by connecting two multi-collectors of the P & P transistor (Q22) to the transistors (Q11) and (Q12) base of the differential amplifier (12), respectively.