KR930001880Y1 - Over load detection circuit at printer's input port - Google Patents

Over load detection circuit at printer's input port Download PDF

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Publication number
KR930001880Y1
KR930001880Y1 KR2019870014313U KR870014313U KR930001880Y1 KR 930001880 Y1 KR930001880 Y1 KR 930001880Y1 KR 2019870014313 U KR2019870014313 U KR 2019870014313U KR 870014313 U KR870014313 U KR 870014313U KR 930001880 Y1 KR930001880 Y1 KR 930001880Y1
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South Korea
Prior art keywords
printer
vcc
detection circuit
terminal
latch
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KR2019870014313U
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Korean (ko)
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KR890005425U (en
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최병환
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주식회사 금성사
최근선
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Priority to KR2019870014313U priority Critical patent/KR930001880Y1/en
Publication of KR890005425U publication Critical patent/KR890005425U/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02—Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers

Abstract

내용 없음.No content.

Description

프린터의 입력단 과부하 검출회로Input terminal overload detection circuit of printer

제1도는 종래의 회로도.1 is a conventional circuit diagram.

제2도는 본 고안에 다른 프린터의 입력단 과부하 검출회로도.2 is an input overload detection circuit diagram of a printer according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 프린터 포트 출력단 2 : 프린터 입력단1: Printer port output terminal 2: Printer input terminal

3 : 프린터 케이블 4 : 콘트롤라인3: printer cable 4: control line

5 : 전원분배부 6 : 과부하 감지부5: power distribution unit 6: overload detection unit

IC1, IC3: 래치 IC3, IC4, IC6: 버퍼IC 1 , IC 3 : Latch IC 3 , IC 4 , IC 6 : Buffer

IC5: CMOS TTL래치 Q1: 트랜지스터IC 5 : CMOS TTL Latch Q 1 : Transistor

R1-R9: 저항R 1 -R 9 : resistance

본 고안은 프린터(Printer)의 출력단에 프린터를 연결하여 사용하는 회로에 관한 것으로, 특히 프린터 포트 출력단에 CMOS TTL IC회로를 사용하여 전송케이블 또는 프린터 입력단의 쇼트 등으로 인해 과전류가 인가되는 것을 방지시키도록 한 프린터의 입력단 과부하 검출회로에 관한 것이다.The present invention relates to a circuit used by connecting a printer to an output terminal of a printer. In particular, a CMOS TTL IC circuit is used at the output port of a printer to prevent overcurrent from being applied due to a short of a transmission cable or a printer input terminal. An input terminal overload detection circuit of a printer.

종래의 회로구성은 제1도에서 보는 바와 같이 PC또는 단말기 등의 프린터 포트 출력단(1)에 있는 래치(IC1)와 버퍼(IC2)가 프린터 케이블(3)과 콘트롤라인(4)에 의해 프린터 입력단(2)의 래치(IC3)와 버퍼(IC4)에 각각 접속되어 있는 구성으로, 그의 동작 상태를 살펴보면, 래치(IC1)로 인가되는 데이타를 프린터 케이블(3)을 통해 프린터 입력단(2)의 래치(IC3)에 인가하여 일시 저장한 후 전송하고 콘트롤라인(4)을 통해 데이타의 전송과 수신을 하도록 되어 있는데, 종래의 기술은 단순히 데이타만을 송,수신하도록 되어 있어 전송 케이블이나 프린터 입력단의 쇼트시 과전류가 흘러 에라 데이타(Error Data)가 전송되어도 이를 감지하지 못하게 되어 기기의 손상을 초래하게 되는 문제점이 있었다.In the conventional circuit configuration, as shown in FIG. 1, the latch IC 1 and the buffer IC 2 in the printer port output terminal 1 of the PC or the terminal are connected by the printer cable 3 and the control line 4. The configuration is connected to the latch (IC 3 ) and the buffer (IC 4 ) of the printer input terminal (2), respectively, when looking at the operation state, the data input to the latch (IC 1 ) through the printer cable (3) printer input terminal It is applied to the latch (IC 3 ) of (2) to temporarily store and transmit the data, and to transmit and receive data through the control line (4). In the conventional technology, only the data is transmitted and received. However, when the input current of the printer is shorted, over current flows and error data is transmitted, thereby preventing the detection of the device and causing damage to the device.

이에 본 고안은 상기한 문제점을 개선시키기 위해 안출된 것으로서, 프린터 포트 출력단에 전류의 변동에 민감한 CMOS TTL을 사용한 래치를 구성시키고, CMOS TTL IC의 전원입력단에 트랜지스터와 저항 및 콘덴서의 과전류 검출회로를 연결하여 과전류 인가시에 CPU를제어시키도록 한 것으로, 이하 그 회로구성을 첨부된 도면에 따라 설명하면 다음과 같다.In order to solve the above problems, the present invention is designed to construct a latch using a CMOS TTL that is sensitive to a change in current at an output port of a printer port, and to provide an overcurrent detection circuit of a transistor, a resistor, and a capacitor at a power input of a CMOS TTL IC. The CPU is controlled when the overcurrent is applied by connecting the circuit configuration according to the accompanying drawings.

제2도는 본 고안에 따른 프린터의 입력단과 부하 검출회로를 나타낸 것으로 프린터의 입력단 부하 검출회로는 PC 또는 단말기 등의 프린터 포트 출력단(1)에 설치된 CMOS TTL 래치부(IC5), 상기 CMOS TTL 래치부(IC5)의 출력데이타를 프린터 케이블(3)을 통해 수신하는 프린터 입력단(2)의 래치부(IC3), 상기 CMOS TTL 래치부(IC5)의 전원단에 일측이 연결되는 타측이 접지된 콘덴서(C1), 전원(Vcc)에 직렬로 연결된 두개의 저항(R1,R2)으로 구성되어 상기 전원(Vcc)을 분압하고 분배된 전압(Vcc1)을 상기 CMOS TTL 래치부(IC5)의 전원단에 인가하는 전원분배부(5), 상기 전원분배부(5)에 의해 분배된 전압(Vcc-Vcc1)이 베이스단에 인가되고 에미터단에 전원(Vcc)이 접속되며 콜렉터 저항(R3)을 구비한 트랜지스터(Q1)를 포함하여 구성된 과부하 감지부(6), 상기 과부하 감지부(6)의 출력신호를 수신하여 CPU 제어단에 과부하검출 여부를 전송하는 버퍼(IC6)로 구성되며 작용효과를 첨부된 도면에 따라 설명하면 다음과 같다.2 shows an input stage and a load detection circuit of a printer according to the present invention. The input stage load detection circuit of a printer includes a CMOS TTL latch unit IC 5 installed at a printer port output terminal 1 such as a PC or a terminal, and the CMOS TTL latch. The other side of which one side is connected to the latch unit IC 3 of the printer input terminal 2 and the power terminal of the CMOS TTL latch unit IC 5 , which receives the output data of the unit IC 5 through the printer cable 3. A grounded capacitor C 1 and two resistors R 1 and R 2 connected in series to a power supply Vcc divide the power supply Vcc and divide the divided voltage Vcc 1 into the CMOS TTL latch unit. The power distribution unit 5 applied to the power supply terminal of IC 5 , the voltage Vcc-Vcc 1 distributed by the power distribution unit 5 is applied to the base terminal, and the power supply Vcc is connected to the emitter terminal. And an overload detector 6 including a transistor Q 1 having a collector resistor R 3 , the overload detector It consists of a buffer (IC 6 ) for receiving the output signal of (6) and transmits whether or not overload detection to the CPU control stage, the operation effect will be described according to the accompanying drawings as follows.

단말기의 프린터 포트 출력단에서 CMOS TTL 래치(IC5)의 입력단으로 데이타가 인가되면 그 데이타는 프린터 케이블(3)을 통해 프린터 입력단의 래치(IC3)로 전송되게 된다.When data is applied from the printer port output terminal of the terminal to the input terminal of the CMOS TTL latch IC 5 , the data is transmitted to the latch IC 3 of the printer input terminal through the printer cable 3.

정상동작시 프린터 입력단 래치(IC3)의 입력전류는 극소량(수 mA)의 전류가 소비되는데 이는 CMOS TTL 래치(IC5)에서 공급받게 된다.In normal operation, the input current of the printer input latch (IC 3 ) consumes a very small amount (a few mA) of current, which is supplied by the CMOS TTL latch (IC5).

그러나 전송케이블(3) 또는 프린터 입력단 쇼트 등의 이상동작으로 과전류가 인가될 시에는 래치(IC3)의 소비전력이 증가하므로 CMOS TTL 래치(IC5)로 인가되는 전원분배부(5)의 전루(ia)가 정상 동작시보다 증가하여 전류(ia+ib)만큼 흐르게 된다.However, when overcurrent is applied due to abnormal operation such as transmission cable 3 or printer input terminal short, power consumption of the latch IC 3 increases, so that the power distribution part 5 applied to the CMOS TTL latch IC 5 is applied. (ia) increases more than normal operation and flows by current (ia + ib).

따라서 저항(R1)의 양단전압(VR1)이 증가하여 VT의 전압이(R1Xib)만큼 감소하게 되므로 상기 과부하 감지부(6)의 트랜지스터(Q1)의 베이스에는 로우(L) 전원이 인가되게 된다.Therefore, since the voltage VR 1 of both ends of the resistor R 1 is increased to decrease the voltage of V T by R 1 Xib, the low L is applied to the base of the transistor Q 1 of the overload detector 6. Power will be applied.

상기에 따라 트랜지스터(Q1)는 구동되어 전원(Vcc)의 하이(H) 전압이 트랜지스터(Q1)와 버퍼(IC6)를 거쳐 CPU는 이를 감지함으로써 과부하 상태를 인식하여 프린터 입력단으로의 데이타전송을 중지시키며 동시에 기기의 모든 기능을 중지시켜 기기의 손상을 방지할 수 있게 된다.According to the above, the transistor Q 1 is driven so that the high (H) voltage of the power supply Vcc passes through the transistor Q 1 and the buffer IC 6 , and the CPU detects the overload condition. You can stop the transmission and at the same time stop all the functions of the device to prevent damage to the device.

따라서 본 고안에 따른 프린터의 입력단 과부하 검출회로는 이상의 설명에서와 같이 프린터 포트 출력단에 전류의 변동에 민감한 CMOS TTL 래치를 구성시켜 과전류 인가시 과전류 검출회로로 CPU를 제어하여 기기의 동작을 중단시킴으로써 기기의 손상을 방지시키고 수명을 연장시키는 효과를 갖게 된다.Therefore, the input overload detection circuit of the printer according to the present invention configures a CMOS TTL latch sensitive to the change of current at the output port of the printer port as described above, and stops the operation of the device by controlling the CPU with the overcurrent detection circuit when the overcurrent is applied. It has the effect of preventing damage and extending the life.

Claims (1)

프린터 출력단에 프린터를 연결하여 사용하는 회로에 있어서, 단말기의 프린터 포트 출력으로부터 데이타를 입력받아 CMOS TTL 래치부(IC5), 프린터 케이블(3)을 통해 상기 CMOS TTL 래치부(IC5)의 데이타를 수신하여 일시 저장한 후 전송하는 래치부(IC3), 전원(Vcc)을 인가받아 상기 CMOS TTL 래치부(IC5)의 전원단에 분배된 전압(Vcc1)을 인가하는 전원분배부(5), 상기 전원 분배부(5)에 의해 전원(Vcc)이 분배된 전압(Vcc-Vcc1)이 인가되며 상기전압(Vcc-Vcc1)레벨에 따라 과부하 여부를 검출, CPU제어단에 데이타 전송 중지신호를 과부하 감지부(6)로 구성됨을 특징을 하는 프린터의 입력단 과부하 검출회로.In a circuit used by connecting a printer to a printer output terminal, the data is received from the printer port output of the terminal to receive data from the CMOS TTL latch unit (IC 5 ) through the CMOS TTL latch unit (IC 5 ) and the printer cable (3). The power distribution unit for receiving and temporarily storing and transmitting the latch unit IC 3 and the power supply Vcc and applying the voltage Vcc 1 distributed to the power supply terminal of the CMOS TTL latch unit IC 5 . 5) The voltage Vcc-Vcc 1 to which the power supply Vcc is distributed by the power distribution unit 5 is applied, and whether or not an overload is detected according to the voltage Vcc-Vcc 1 level is detected. Input overload detection circuit of the printer, characterized in that the transmission stop signal consisting of an overload detection unit (6).
KR2019870014313U 1987-08-26 1987-08-26 Over load detection circuit at printer's input port KR930001880Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019870014313U KR930001880Y1 (en) 1987-08-26 1987-08-26 Over load detection circuit at printer's input port

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Application Number Priority Date Filing Date Title
KR2019870014313U KR930001880Y1 (en) 1987-08-26 1987-08-26 Over load detection circuit at printer's input port

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KR890005425U KR890005425U (en) 1989-04-20
KR930001880Y1 true KR930001880Y1 (en) 1993-04-16

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KR2019870014313U KR930001880Y1 (en) 1987-08-26 1987-08-26 Over load detection circuit at printer's input port

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