KR930001640A - Processor test method - Google Patents

Processor test method Download PDF

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Publication number
KR930001640A
KR930001640A KR1019910009974A KR910009974A KR930001640A KR 930001640 A KR930001640 A KR 930001640A KR 1019910009974 A KR1019910009974 A KR 1019910009974A KR 910009974 A KR910009974 A KR 910009974A KR 930001640 A KR930001640 A KR 930001640A
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KR
South Korea
Prior art keywords
test
normal
checking
processor
executing
Prior art date
Application number
KR1019910009974A
Other languages
Korean (ko)
Inventor
윤희선
Original Assignee
정용문
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019910009974A priority Critical patent/KR930001640A/en
Publication of KR930001640A publication Critical patent/KR930001640A/en

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Abstract

내용 없음No content

Description

프로세서 테스트 방법Processor test method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용되는 프로세서의 블럭도.1 is a block diagram of a processor to which the present invention is applied.

제2도는 본 발명의 흐름도.2 is a flow chart of the present invention.

Claims (1)

교환기 시스템에 있어서, 각 플래그의 비트를 세트하고 이들에 따른 브랜치를 실시하는 제1과정과, 정상적으로 브랜치한 경우 쉬프트 명령을 실행하여 레지스터들의 정상 동작여부를 검사하는 제2과정과, 정상적인 쉬프트 명령 실행시 데이타 전송 검사를 실시하는 제3과정과, 데이타 전송 검사결과가 정상적일시 정수 덧셈 루프테스트를 실시하는 제4과정과, 정상 곱셈 테스트를 실시하여 속도 및 연산시의 에러를 체크하는 제5과정과, 명령어 조합 시험을 실시하는 제6과정과, 메모리 억세스 속도를 검사하는 제7과정과, 문자열 정렬과 이동 테스트 작업을 실시하는 제8과정과, 부동 소숫점 연산 시험을 실시하여 프로세서의 처리 속도를 검사하는 제9과정으로 이루어짐을 특징으로 하는 프로세서 테스트 방법.In the switch system, a first process of setting bits of each flag and performing a branch according to the flags, a second process of executing a shift instruction in a normal branch, and checking whether the registers operate normally, and executing a normal shift instruction A third step of performing a time data transmission test; a fourth step of performing an integer addition loop test when the data transmission test result is normal; a fifth step of checking a speed and an error during a calculation by performing a normal multiplication test; A sixth step of performing an instruction combination test, a seventh step of checking a memory access speed, an eighth step of performing a string alignment and a moving test operation, and a floating point arithmetic test to check a processor's processing speed Processor test method, characterized in that made in the ninth process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009974A 1991-06-17 1991-06-17 Processor test method KR930001640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910009974A KR930001640A (en) 1991-06-17 1991-06-17 Processor test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009974A KR930001640A (en) 1991-06-17 1991-06-17 Processor test method

Publications (1)

Publication Number Publication Date
KR930001640A true KR930001640A (en) 1993-01-16

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ID=67440924

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009974A KR930001640A (en) 1991-06-17 1991-06-17 Processor test method

Country Status (1)

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KR (1) KR930001640A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100649794B1 (en) * 2000-02-18 2006-11-24 가부시키가이샤 파이오락꾸스 Rotary damper

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100649794B1 (en) * 2000-02-18 2006-11-24 가부시키가이샤 파이오락꾸스 Rotary damper

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