KR930001575A - Substrate Voltage Generator - Google Patents

Substrate Voltage Generator Download PDF

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Publication number
KR930001575A
KR930001575A KR1019910009657A KR910009657A KR930001575A KR 930001575 A KR930001575 A KR 930001575A KR 1019910009657 A KR1019910009657 A KR 1019910009657A KR 910009657 A KR910009657 A KR 910009657A KR 930001575 A KR930001575 A KR 930001575A
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KR
South Korea
Prior art keywords
terminal
node
pumping capacitor
mos transistor
source
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KR1019910009657A
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Korean (ko)
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KR940003405B1 (en
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이영택
민병혁
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김광호
삼성전자 주식회사
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Priority to KR1019910009657A priority Critical patent/KR940003405B1/en
Publication of KR930001575A publication Critical patent/KR930001575A/en
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Publication of KR940003405B1 publication Critical patent/KR940003405B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dc-Dc Converters (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

기판전압 발생장치Substrate Voltage Generator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 기판전압 발생 장치의 전체 시스템 블럭도.1 is an overall system block diagram of a substrate voltage generator.

제2도는 종래에 있어서의 차아지 펌프 회로도.2 is a conventional charge pump circuit diagram.

제3도는 종래에 있어서의 차아지 펌프 회로의 동작 타이밍도.3 is an operation timing diagram of a charge pump circuit in the related art.

제4도는 본 발명에 따른 차아지 펌프 회로도.4 is a charge pump circuit diagram according to the present invention.

제5도는 본 발명에 따른 차아지 펌프 회로의 동작 타이밍도.5 is an operation timing diagram of a charge pump circuit according to the present invention.

Claims (5)

서로 반전되는 두개의 제1 및 제2구형파를 입력하고 출력단이 기판 전압단에 접속되어 상기 기판 전압단을 음전압으로 만들어주는 기판전압 발생 장치의 차아지 펌프회로에 있어서, 한쪽 전극이 상기 제1구형파에 연결된 제1펌핑 캐패시터(11)와, 한쪽 전극이 상기 제1구형파에 연결된 제2펌핑 캐패시터(12)와, 한쪽 전극이 상기 제2구형파에 연결된 제3펌핑 캐패시터(13)와, 한쪽 전극이 상기 제2구형파에 연결된 제4펌핑 캐패시터(14)와, 소오스단자와 드레인단자가 상기 제1펌핑 캐패시터(11) 및 제2펌핑 캐패시터(12)의 다른쪽 전극 사이에 접속되고 게이트가 상기 출력단에 접속된 제1모오스 트랜지스터(15)와, 소오스단자와 드레인단자가 상기 제3펌핑 캐패시터(13) 및 제4펌핑 캐패시터(14)의 다른쪽 전극 사이에 접속되고 게이트가 상기 출력단에 접속된 제2피모오스 트랜지스터(16)와, 상기 제1, 제2, 제3 및 제4펌핑 캐패시터(11)(12)(13)(14)와 상기 출력단 사이에 접속되어 상기 출력단의 전위를 소정의 상태로 제어하기 위한 수단을 구비함을 특징으로 하는 차아지 펌프회로.In the charge pump circuit of a substrate voltage generating device for inputting two first and second square waves inverted from each other and having an output terminal connected to a substrate voltage terminal, the substrate voltage terminal becomes a negative voltage. A first pumping capacitor 11 connected to a square wave, a second pumping capacitor 12 connected to one of the first square waves, a third pumping capacitor 13 connected to one of the second square waves, and one electrode A fourth pumping capacitor 14 connected to the second square wave, a source terminal and a drain terminal are connected between the other electrode of the first pumping capacitor 11 and the second pumping capacitor 12 and a gate is connected to the output terminal; A first MOS transistor 15 connected to the first source source, a source terminal and a drain terminal connected between the other electrodes of the third pumping capacitor 13 and the fourth pumping capacitor 14 and a gate connected to the output terminal. 2 feet It is connected between the MOS transistor 16 and the said 1st, 2nd, 3rd, and 4th pumping capacitors 11, 12, 13, 14, and the output terminal, and controls the electric potential of the output terminal to a predetermined state. A charge pump circuit, comprising means for 제1항에 있어서, 상기 제1, 제2, 제3 및 제4펌핑 캐패시터(11)(12)(13)(14)가 각각 피모오스 트랜지스터로 구성됨을 특징으로 하는 차아지 펌프회로.The charge pump circuit according to claim 1, wherein said first, second, third and fourth pumping capacitors (11) (12) (13) (14) are each composed of PMOS transistors. 제1항에 있어서, 상기 제1 및 제2모오스 트랜지스터(15)(16)가 피모오스 트랜지스터로 구성됨을 특징으로 하는 차아지 펌프회로.The charge pump circuit as set forth in claim 1, wherein said first and second MOS transistors (15, 16) comprise PMOS transistors. 제1항에 있어서, 상기 수단이 상기 제1펌핑 캐패시터(11)와 상기 제1모오스 트랜지스터(15)를 연결하는 제1노드(A)와, 상기 제2펌핑 캐패시터(12)와 상기 제1모오스 트랜지스터(15)를 연결하는 제2노드(B)와, 상기 제3펌핑 캐패시터(13)와 상기 제2모오스 트랜지스터(16)를 연결하는 제3노드(C)와, 상기 제4펌핑 캐패시터(14)와 상기 제2모오스 트랜지스터(16)를 접속하는 제4노드(D)와, 소오스단자와 드레인단자가 상기 제1노드(A)와 상기 출력단에 접속되고 게이트가 상기 제1노드(A)에 접속된 제3모오스 트랜지스터(17)와, 소오스단자와 드레인단자가 상기 제1노드(A)와 접지전압단에 접속되고 게이트가 상기 제4노드(D)에 접속된 제4모오스 트랜지스터(18)와, 소오스단자와 드레인단자가 상기 제3노드(C)와 접지전압단에 접속되고 게이트가 상기 제2노드(B)에 접속된 제5모오스 트랜지스터(19)와, 소오스단자와 드레인단자가 상기 제3노드(C)와 상기 출력단에 접속되고 게이트가 상기 제3노드(C)에 접속된 제6모오스 트랜지스터(20)로 구성됨을 특징으로 하는 차아지 펌프회로.The method of claim 1, wherein the means comprises a first node (A) connecting the first pumping capacitor (11) and the first MOS transistor (15), the second pumping capacitor (12) and the first MOS A second node B connecting the transistor 15, a third node C connecting the third pumping capacitor 13 and the second MOS transistor 16, and the fourth pumping capacitor 14. ) And a fourth node D connecting the second MOS transistor 16, a source terminal and a drain terminal are connected to the first node A and the output terminal, and a gate is connected to the first node A. A fourth MOS transistor 18 having a third MOS transistor 17 connected thereto, a source terminal and a drain terminal connected to the first node A and a ground voltage terminal, and a gate connected to the fourth node D. And a fifth module in which a source terminal and a drain terminal are connected to the third node C and the ground voltage terminal, and a gate thereof is connected to the second node B. And a sixth MOS transistor 20 having a source transistor 19, a source terminal and a drain terminal connected to the third node C and the output terminal, and a gate connected to the third node C. Charge pump circuit. 제4항에 있어서, 상기 제3, 제4, 제5 및 제6모오스 트랜지스터(17)(18)(19)(20)가 피모오스 트랜지스터로 구성됨을 특징으로 하는 차아지 펌프회로.5. The charge pump circuit according to claim 4, wherein the third, fourth, fifth and sixth MOS transistors (17) (18) (19) (20) are composed of PMOS transistors. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009657A 1991-06-12 1991-06-12 Substrate-voltage generator device KR940003405B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910009657A KR940003405B1 (en) 1991-06-12 1991-06-12 Substrate-voltage generator device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009657A KR940003405B1 (en) 1991-06-12 1991-06-12 Substrate-voltage generator device

Publications (2)

Publication Number Publication Date
KR930001575A true KR930001575A (en) 1993-01-16
KR940003405B1 KR940003405B1 (en) 1994-04-21

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KR1019910009657A KR940003405B1 (en) 1991-06-12 1991-06-12 Substrate-voltage generator device

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KR100991804B1 (en) * 2008-06-10 2010-11-04 유한회사 마스터이미지쓰리디아시아 Stereoscopic Image Generation Chip For Mobile Equipment, and Method For Generating Stereoscopic Image Using The Same

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