KR930001329U - Information processing device with cache memory piggy board - Google Patents

Information processing device with cache memory piggy board

Info

Publication number
KR930001329U
KR930001329U KR2019910008951U KR910008951U KR930001329U KR 930001329 U KR930001329 U KR 930001329U KR 2019910008951 U KR2019910008951 U KR 2019910008951U KR 910008951 U KR910008951 U KR 910008951U KR 930001329 U KR930001329 U KR 930001329U
Authority
KR
South Korea
Prior art keywords
information processing
processing device
cache memory
piggy
board
Prior art date
Application number
KR2019910008951U
Other languages
Korean (ko)
Other versions
KR930005477Y1 (en
Inventor
이태엽
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019910008951U priority Critical patent/KR930005477Y1/en
Publication of KR930001329U publication Critical patent/KR930001329U/en
Application granted granted Critical
Publication of KR930005477Y1 publication Critical patent/KR930005477Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
    • G06F2015/765—Cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR2019910008951U 1991-06-17 1991-06-17 Data processor with a piggy board of cache memory KR930005477Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019910008951U KR930005477Y1 (en) 1991-06-17 1991-06-17 Data processor with a piggy board of cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019910008951U KR930005477Y1 (en) 1991-06-17 1991-06-17 Data processor with a piggy board of cache memory

Publications (2)

Publication Number Publication Date
KR930001329U true KR930001329U (en) 1993-01-21
KR930005477Y1 KR930005477Y1 (en) 1993-08-20

Family

ID=19315212

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019910008951U KR930005477Y1 (en) 1991-06-17 1991-06-17 Data processor with a piggy board of cache memory

Country Status (1)

Country Link
KR (1) KR930005477Y1 (en)

Also Published As

Publication number Publication date
KR930005477Y1 (en) 1993-08-20

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