KR920020491A - Readout Circuit of Semiconductor Memory - Google Patents

Readout Circuit of Semiconductor Memory Download PDF

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Publication number
KR920020491A
KR920020491A KR1019920005307A KR920005307A KR920020491A KR 920020491 A KR920020491 A KR 920020491A KR 1019920005307 A KR1019920005307 A KR 1019920005307A KR 920005307 A KR920005307 A KR 920005307A KR 920020491 A KR920020491 A KR 920020491A
Authority
KR
South Korea
Prior art keywords
data
information holding
semiconductor memory
readout circuit
selection
Prior art date
Application number
KR1019920005307A
Other languages
Korean (ko)
Other versions
KR100225551B1 (en
Inventor
마사유끼 미야바야시
Original Assignee
오가 노리오
소니 가부시기가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR920020491A publication Critical patent/KR920020491A/en
Application granted granted Critical
Publication of KR100225551B1 publication Critical patent/KR100225551B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

반도체기억장치의 독출회로Readout Circuit of Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본원 발명의 반도체억장치의 독출회로의 제1의 실시예의 회로도,1 is a circuit diagram of a first embodiment of a readout circuit of a semiconductor memory device of the present invention;

제2도는 본원 발명의 반도체기억장치의 독출회로의 제1의 실시예의 주요동작을 설명하는 타임차트.2 is a time chart for explaining the main operation of the first embodiment of the read circuit of the semiconductor memory device of the present invention.

Claims (1)

복수의 기억수단에 기억된 데이터를 선택적으로 독출하는 제1의 선택수단과, 상기 선택수단에 의해 독출된 데이터를 유지하는 제1의 정보유지 수단과, 상기 제1의 정보유지수단에 유지된 데이터를 외부클록에 동기하여 전송하는 전송수단과, 상기 전송수단으로부터의 데이터를 유지하는 제2의 정보유지수단과, 상기 제2의 정보유지수단에 유지된 데이터를 출력포트에 선택적으로 출력하는 제2의 선택수단과, 상기 제1의 선택수단에 의해 데이터가 독출되는 라인을 프리세트하는 프리세트수단을 구비하는 것을 특징으로 하는 반도체기억장치의 독출회로.First selection means for selectively reading out data stored in the plurality of storage means, first information holding means for holding data read by the selection means, and held in the first information holding means. Transmission means for transmitting data in synchronization with an external clock, second information holding means for holding data from the transmission means, and second outputting means for selectively outputting data held in the second information holding means to an output port. And a preset means for presetting a line from which data is read by said first selection means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920005307A 1991-04-02 1992-03-31 Read-out circuit of semiconductor memory device KR100225551B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-098024 1991-04-02
JP09802491A JP3160930B2 (en) 1991-04-02 1991-04-02 Readout circuit of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR920020491A true KR920020491A (en) 1992-11-21
KR100225551B1 KR100225551B1 (en) 1999-10-15

Family

ID=14208353

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920005307A KR100225551B1 (en) 1991-04-02 1992-03-31 Read-out circuit of semiconductor memory device

Country Status (2)

Country Link
JP (1) JP3160930B2 (en)
KR (1) KR100225551B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100713981B1 (en) * 2000-10-10 2007-05-03 주식회사 하이닉스반도체 Method for reading out data of a memory cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100713981B1 (en) * 2000-10-10 2007-05-03 주식회사 하이닉스반도체 Method for reading out data of a memory cell

Also Published As

Publication number Publication date
JP3160930B2 (en) 2001-04-25
JPH04305895A (en) 1992-10-28
KR100225551B1 (en) 1999-10-15

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