KR920015760U - Memory device inspection circuit - Google Patents
Memory device inspection circuitInfo
- Publication number
- KR920015760U KR920015760U KR2019910000175U KR910000175U KR920015760U KR 920015760 U KR920015760 U KR 920015760U KR 2019910000175 U KR2019910000175 U KR 2019910000175U KR 910000175 U KR910000175 U KR 910000175U KR 920015760 U KR920015760 U KR 920015760U
- Authority
- KR
- South Korea
- Prior art keywords
- memory device
- inspection circuit
- device inspection
- circuit
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910000175U KR970007073Y1 (en) | 1991-01-09 | 1991-01-09 | Test circuit of memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019910000175U KR970007073Y1 (en) | 1991-01-09 | 1991-01-09 | Test circuit of memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920015760U true KR920015760U (en) | 1992-08-17 |
KR970007073Y1 KR970007073Y1 (en) | 1997-07-15 |
Family
ID=19309545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019910000175U KR970007073Y1 (en) | 1991-01-09 | 1991-01-09 | Test circuit of memory device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970007073Y1 (en) |
-
1991
- 1991-01-09 KR KR2019910000175U patent/KR970007073Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR970007073Y1 (en) | 1997-07-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20041101 Year of fee payment: 8 |
|
LAPS | Lapse due to unpaid annual fee |