KR920015269A - Subcoding Circuit of Recording and Reproduction Digital System - Google Patents

Subcoding Circuit of Recording and Reproduction Digital System Download PDF

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Publication number
KR920015269A
KR920015269A KR1019910001865A KR910001865A KR920015269A KR 920015269 A KR920015269 A KR 920015269A KR 1019910001865 A KR1019910001865 A KR 1019910001865A KR 910001865 A KR910001865 A KR 910001865A KR 920015269 A KR920015269 A KR 920015269A
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KR
South Korea
Prior art keywords
subcode
signal
error detection
detection code
frame
Prior art date
Application number
KR1019910001865A
Other languages
Korean (ko)
Other versions
KR930010914B1 (en
Inventor
조헌철
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019910001865A priority Critical patent/KR930010914B1/en
Publication of KR920015269A publication Critical patent/KR920015269A/en
Application granted granted Critical
Publication of KR930010914B1 publication Critical patent/KR930010914B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

내용 없음No content

Description

기록재생 디지탈 시스템의 서브코딩회로Subcoding Circuit of Recording and Reproduction Digital System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

세2도는 본 발명의 의한 기록가능한 CD 시스템의 기록계의 블럭도, 제3도는 본 발명에 의한 서브코딩회로의 블럭도, 제4도는 본 발명에 의한 서브코딩회로의 바람직한 일 실시예의 상세회로도.3 is a block diagram of a recording system of a recordable CD system according to the present invention, FIG. 3 is a block diagram of a subcoding circuit according to the present invention, and FIG. 4 is a detailed circuit diagram of a preferred embodiment of the subcoding circuit according to the present invention.

Claims (1)

1bit의 서브코드동기신호와, mbit의 서브코드와, 이 서브코드의 오류검출을 위한 nbit의 오류검출로코드로 이루어진 서브코드신호의 각 bit를 포함하는 한 신볼데이타를, 복수의 심볼데이타로 이루어진 프레임마다 실어서 기록하는 시스템에 있어서, 상기 mbit의 서브코드를 상기 nbit의 오류검출코드의 전송기간 동안에 직렬입력하고 서브코드 전송기간동안에 입력된 서브코드를 직렬 출력하는 시프트레지스트; 상기 시프트레지스트로부터 mbit의 서브코드를 접속하고 상기 nbit의 오류검출코드를 생성하고 mbit의 서브코드와 nbit의 오류검출 코드를 매 프레임의 프레임동기신호 다음에 출력하는 오류검출코드 발생수단; 상기 서브코드신호가 실리는 프레임을 계수하여 상기 서브코드 신호의 첫머리를 나타내는 1bit의 서브코드동기신호를 생성하고 서브코드동기신호가 실리는 프레임의 프레임동기신호 다음에 생성된 1bit의 서브코드동기신호를 출력하는 타이밍회로수단을 구비한 것을 특징으로 하는 기록재생 디지탈 시스템의 서브코딩회로.Synchronous data consisting of a plurality of symbol data includes one bit of a subcode synchronous signal, a mbit subcode, and each bit of a subcode signal composed of nbit error detection code for error detection of the subcode. A system for loading and recording every frame, comprising: a shift register for serially inputting a subcode of mbit during a transmission period of an error detection code of nbit and serially outputting a subcode input during a subcode transmission period; Error detection code generating means for connecting an mbit subcode from the shift register, generating an nbit error detection code, and outputting an mbit subcode and nbit error detection code after each frame synchronization signal; A 1-bit subcode sync signal generated after the frame sync signal of the frame on which the subcode signal is carried by generating a 1-bit subcode sync signal representing the beginning of the subcode signal by counting a frame carrying the subcode signal; And a timing circuit means for outputting a subcoding circuit of a recording / reproducing digital system. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910001865A 1991-01-31 1991-01-31 Sub-coding circuit of recording and reproducing system KR930010914B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910001865A KR930010914B1 (en) 1991-01-31 1991-01-31 Sub-coding circuit of recording and reproducing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910001865A KR930010914B1 (en) 1991-01-31 1991-01-31 Sub-coding circuit of recording and reproducing system

Publications (2)

Publication Number Publication Date
KR920015269A true KR920015269A (en) 1992-08-26
KR930010914B1 KR930010914B1 (en) 1993-11-17

Family

ID=19310711

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910001865A KR930010914B1 (en) 1991-01-31 1991-01-31 Sub-coding circuit of recording and reproducing system

Country Status (1)

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KR (1) KR930010914B1 (en)

Also Published As

Publication number Publication date
KR930010914B1 (en) 1993-11-17

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