KR920014064U - 데드타임 보상회로 - Google Patents

데드타임 보상회로

Info

Publication number
KR920014064U
KR920014064U KR2019900021402U KR900021402U KR920014064U KR 920014064 U KR920014064 U KR 920014064U KR 2019900021402 U KR2019900021402 U KR 2019900021402U KR 900021402 U KR900021402 U KR 900021402U KR 920014064 U KR920014064 U KR 920014064U
Authority
KR
South Korea
Prior art keywords
compensation circuit
dead time
time compensation
dead
circuit
Prior art date
Application number
KR2019900021402U
Other languages
English (en)
Other versions
KR950000620Y1 (ko
Inventor
김규찬
Original Assignee
금성계전 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성계전 주식회사 filed Critical 금성계전 주식회사
Priority to KR2019900021402U priority Critical patent/KR950000620Y1/ko
Publication of KR920014064U publication Critical patent/KR920014064U/ko
Application granted granted Critical
Publication of KR950000620Y1 publication Critical patent/KR950000620Y1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Inverter Devices (AREA)
KR2019900021402U 1990-12-28 1990-12-28 데드타임 보상회로 KR950000620Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900021402U KR950000620Y1 (ko) 1990-12-28 1990-12-28 데드타임 보상회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019900021402U KR950000620Y1 (ko) 1990-12-28 1990-12-28 데드타임 보상회로

Publications (2)

Publication Number Publication Date
KR920014064U true KR920014064U (ko) 1992-07-27
KR950000620Y1 KR950000620Y1 (ko) 1995-02-04

Family

ID=19308132

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019900021402U KR950000620Y1 (ko) 1990-12-28 1990-12-28 데드타임 보상회로

Country Status (1)

Country Link
KR (1) KR950000620Y1 (ko)

Also Published As

Publication number Publication date
KR950000620Y1 (ko) 1995-02-04

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
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FPAY Annual fee payment

Payment date: 20030103

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee