KR920013898A - Automatic Gain Control Method and Circuit of Transistor - Google Patents

Automatic Gain Control Method and Circuit of Transistor Download PDF

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Publication number
KR920013898A
KR920013898A KR1019900021772A KR900021772A KR920013898A KR 920013898 A KR920013898 A KR 920013898A KR 1019900021772 A KR1019900021772 A KR 1019900021772A KR 900021772 A KR900021772 A KR 900021772A KR 920013898 A KR920013898 A KR 920013898A
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KR
South Korea
Prior art keywords
gain control
automatic gain
transistor
control method
circuit
Prior art date
Application number
KR1019900021772A
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Korean (ko)
Inventor
음두찬
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019900021772A priority Critical patent/KR920013898A/en
Publication of KR920013898A publication Critical patent/KR920013898A/en

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Abstract

내용 없음No content

Description

트랜지스터의 자동 이득제어 방법 및 회로Automatic Gain Control Method and Circuit of Transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 자동 이득제어 방법을 설명하기 위한 회로도이다. 제2도는 제1도에 도시된 회로를 이등분회로 개념에 의해 간단히한 회로도이다.1 is a circuit diagram for explaining the automatic gain control method according to the present invention. FIG. 2 is a circuit diagram of the circuit shown in FIG.

Claims (3)

트랜지스터의 포화영역과 활성영역에서의 등가저항의 차이를 이용하여 이득을 제어하는 것을 특징으로 하는 자동이득 제어방법.An automatic gain control method comprising controlling gain by using a difference between equivalent resistances in a saturation region and an active region of a transistor. 전원(Vcc)에 연결된 부하저항(R1,R2)과, 트랜지스터(Q1,Q2)를 구비한 차동증폭기에 있어서, 상기 차동증폭기의 트랜지스터(Q1,Q2)와 바이어스 전류원(IEE)사이에 이득제어용 트랜지스터(Q3,Q4)와 저항(R3,R4)의 각각 접속된 것을 특징으로 하는 자동이득 제어회로.In a differential amplifier with a power supply (Vcc) a load resistance (R 1, R 2) and the transistors (Q 1, Q 2) coupled to the bias current source and the transistor (Q 1, Q 2) of the differential amplifier (I EE) gain control transistors (Q 3, Q 4) and a resistor (R 3, an automatic gain control circuit, characterized in that the connection each R 4) in between. 제2항에 있어서, 상기 이득제어용 저항(R3,R4)은 트랜지스터(Q3,Q4)의 콜렉터와 에미터상이에 각각 접속된 것을 특징으로 하는 자동이득 제어회로.The automatic gain control circuit according to claim 2, wherein the gain control resistors (R 3 , R 4 ) are connected to the collector and the emitter of transistors (Q 3 , Q 4 ), respectively. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021772A 1990-12-26 1990-12-26 Automatic Gain Control Method and Circuit of Transistor KR920013898A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021772A KR920013898A (en) 1990-12-26 1990-12-26 Automatic Gain Control Method and Circuit of Transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021772A KR920013898A (en) 1990-12-26 1990-12-26 Automatic Gain Control Method and Circuit of Transistor

Publications (1)

Publication Number Publication Date
KR920013898A true KR920013898A (en) 1992-07-30

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ID=67538580

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021772A KR920013898A (en) 1990-12-26 1990-12-26 Automatic Gain Control Method and Circuit of Transistor

Country Status (1)

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KR (1) KR920013898A (en)

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