KR920013108U - Data input / output circuit in memory test mode - Google Patents

Data input / output circuit in memory test mode

Info

Publication number
KR920013108U
KR920013108U KR2019900019841U KR900019841U KR920013108U KR 920013108 U KR920013108 U KR 920013108U KR 2019900019841 U KR2019900019841 U KR 2019900019841U KR 900019841 U KR900019841 U KR 900019841U KR 920013108 U KR920013108 U KR 920013108U
Authority
KR
South Korea
Prior art keywords
data input
output circuit
test mode
memory test
memory
Prior art date
Application number
KR2019900019841U
Other languages
Korean (ko)
Other versions
KR930008481Y1 (en
Inventor
김정우
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019900019841U priority Critical patent/KR930008481Y1/en
Publication of KR920013108U publication Critical patent/KR920013108U/en
Application granted granted Critical
Publication of KR930008481Y1 publication Critical patent/KR930008481Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
KR2019900019841U 1990-12-14 1990-12-14 Data input/output circuit for memory test mode KR930008481Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900019841U KR930008481Y1 (en) 1990-12-14 1990-12-14 Data input/output circuit for memory test mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019900019841U KR930008481Y1 (en) 1990-12-14 1990-12-14 Data input/output circuit for memory test mode

Publications (2)

Publication Number Publication Date
KR920013108U true KR920013108U (en) 1992-07-27
KR930008481Y1 KR930008481Y1 (en) 1993-12-22

Family

ID=19307002

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019900019841U KR930008481Y1 (en) 1990-12-14 1990-12-14 Data input/output circuit for memory test mode

Country Status (1)

Country Link
KR (1) KR930008481Y1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102218707B1 (en) * 2017-05-26 2021-02-23 엘에스엠트론 주식회사 Gear connecting structure of engine

Also Published As

Publication number Publication date
KR930008481Y1 (en) 1993-12-22

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