KR920007177U - Input level display circuit of satellite broadcast receiving antenna - Google Patents

Input level display circuit of satellite broadcast receiving antenna

Info

Publication number
KR920007177U
KR920007177U KR2019900014322U KR900014322U KR920007177U KR 920007177 U KR920007177 U KR 920007177U KR 2019900014322 U KR2019900014322 U KR 2019900014322U KR 900014322 U KR900014322 U KR 900014322U KR 920007177 U KR920007177 U KR 920007177U
Authority
KR
South Korea
Prior art keywords
receiving antenna
broadcast receiving
display circuit
input level
level display
Prior art date
Application number
KR2019900014322U
Other languages
Korean (ko)
Other versions
KR930000803Y1 (en
Inventor
권주환
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019900014322U priority Critical patent/KR930000803Y1/en
Publication of KR920007177U publication Critical patent/KR920007177U/en
Application granted granted Critical
Publication of KR930000803Y1 publication Critical patent/KR930000803Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/90—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for satellite broadcast receiving

Landscapes

  • Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Noise Elimination (AREA)
KR2019900014322U 1990-09-18 1990-09-18 Circuit for displaying input level KR930000803Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900014322U KR930000803Y1 (en) 1990-09-18 1990-09-18 Circuit for displaying input level

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019900014322U KR930000803Y1 (en) 1990-09-18 1990-09-18 Circuit for displaying input level

Publications (2)

Publication Number Publication Date
KR920007177U true KR920007177U (en) 1992-04-22
KR930000803Y1 KR930000803Y1 (en) 1993-02-25

Family

ID=19303462

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019900014322U KR930000803Y1 (en) 1990-09-18 1990-09-18 Circuit for displaying input level

Country Status (1)

Country Link
KR (1) KR930000803Y1 (en)

Also Published As

Publication number Publication date
KR930000803Y1 (en) 1993-02-25

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Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20030129

Year of fee payment: 11

LAPS Lapse due to unpaid annual fee