KR920006834A - Digital Video Processing Unit (DVP) - Google Patents

Digital Video Processing Unit (DVP) Download PDF

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Publication number
KR920006834A
KR920006834A KR1019900014957A KR900014957A KR920006834A KR 920006834 A KR920006834 A KR 920006834A KR 1019900014957 A KR1019900014957 A KR 1019900014957A KR 900014957 A KR900014957 A KR 900014957A KR 920006834 A KR920006834 A KR 920006834A
Authority
KR
South Korea
Prior art keywords
circuit
hst
switch switching
terminal
signal
Prior art date
Application number
KR1019900014957A
Other languages
Korean (ko)
Other versions
KR930001467B1 (en
Inventor
김광성
Original Assignee
김광성
주식회사 컴픽스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광성, 주식회사 컴픽스 filed Critical 김광성
Priority to KR1019900014957A priority Critical patent/KR930001467B1/en
Publication of KR920006834A publication Critical patent/KR920006834A/en
Application granted granted Critical
Publication of KR930001467B1 publication Critical patent/KR930001467B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Studio Circuits (AREA)

Abstract

내용 없음.No content.

Description

디지탈 비디오 처리장치(DVP)Digital Video Processing Unit (DVP)

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 회로 구성도.1 is a circuit diagram of the present invention.

제2도는 완충 및 증폭회로 연결도.2 is a connection diagram of the buffer and amplification circuit.

제3도는 플립플롭 구성도.3 is a flip-flop configuration.

제4도는 증폭회로(AMP4)도.4 is an amplification circuit (AMP 4 ).

제5도는 고속스위치 전환 집적회로와 연결된 증폭회로(AMP3)도.5 is an amplifier circuit AMP3 connected to a fast switch switching integrated circuit.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

HST1∼HST2: 고속스위치 전환 집적회로 AMP1∼AMP5: 증폭회로HST 1 to HST 2 : High speed switch switching integrated circuit AMP 1 to AMP 5 : Amplification circuit

2 : 완충회로 3 : 슈퍼임포즈회로2: buffer circuit 3: superimpose circuit

4 : 키회로 5 : 어드레스 분리회로4: key circuit 5: address separation circuit

6 : 스위치 전환 제어회로 7 : 인버터6: switch switching control circuit 7: inverter

9 : 화상신호 10 : 문자 및 그래픽신호9: Image signal 10: Text and graphic signal

Claims (1)

화상신호에 문자 및 그래픽 신호를 오버랩 또는 분리시키는 장치에 있어서, 외부 화상신호를 처리하는 증폭회로(AMP1)를 슈퍼임포즈 회로(3)에 연결하고, 컴퓨터에 내장된 보드의 A1단자와 B1단자를 고속스위치 전환 집적회로(HST1)에 연결하여 고속스위치 전환 집적회로(HST1) 출력의 일측은 완충회로(2)에 일측은 증폭회로(AMP5)에 연결하며, 완충회로(2)의 출력선을 슈퍼임포즈 회로(3)에 접속함으로서 화상신호(9)와 문자 및 그래픽 신호(10)가 순차적으로 증폭회로(AMP2)에 인가되도록 하며, A1단자와 B1단자에서 발생한 키신호를 어드레스 분리회로(5)에 인가하여 여기에서 출력된 신호의 일측은 스위치 전환 제어회로(6)에 일측은 키회로(4)에 연결하고, 스위치 전환회로(6)를 인버터(7)와 연결하여 고속스위치 전환 집적회로(HST1)에 접속하고 키회로(4)는 증폭회로(AMP4)를 지나 슈퍼임포즈 회로(3)에 연결하며 키회로(4)의 펄스신호에 따라 문자나 그래픽 신호가 고속스위치 전환 집적회로(HST1)를 통해 증폭회로(AMP3)에 연결되도록 하고, A2단자 및 B2단자로부터 나온 RGB 색상신호를 고속스위치 전환 집적회로(HST2)를 통해 스위치 제어회로(6)의 출력라인에 접속하여 고속스위치 전환 집적회로(HST1)에 인가함으로서 컴퓨터에서 오는 모든 문자 및 그래픽 신호가 방송신호에 인터페이스 되도록 한 것을 특징으로 하는 디지탈 비디오 처리장치(DVP).In an apparatus for overlapping or separating text and graphic signals from an image signal, an amplifying circuit AMP 1 for processing an external image signal is connected to the superimposition circuit 3, and an A 1 terminal of a board built into a computer is provided. the B 1 terminal high-speed switching integrated circuit high-speed switching integrated by connecting the (HST 1) circuit (HST 1) side of the output side to the buffer circuit (2) and connected to the amplifier circuit (AMP 5), a buffer circuit ( By connecting the output line of 2) to the superimpose circuit 3, the image signal 9 and the character and graphic signals 10 are sequentially applied to the amplifying circuit AMP 2 , and the A 1 terminal and the B 1 terminal. Is applied to the address separation circuit (5), one side of the signal output here is connected to the switch switching control circuit (6) and one side to the key circuit (4), and the switch switching circuit (6) is connected to the inverter ( 7) is connected to the high speed switch switching integrated circuit (HST 1 ) and the key circuit ( 4) is connected to the super-impedance circuit (3) through the amplifier circuit (AMP 4 ), and the character or graphic signal is passed through the high-speed switch switching integrated circuit (HST 1 ) according to the pulse signal of the key circuit (4) (a). AMP 3 ), and the RGB color signals from the A 2 and B 2 terminals are connected to the output line of the switch control circuit 6 through the high speed switch switching integrated circuit (HST 2 ). Digital video processing apparatus (DVP), characterized in that all character and graphic signals from a computer are interfaced to a broadcast signal by applying to HST 1 ). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900014957A 1990-09-20 1990-09-20 Apparatus for dvp KR930001467B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900014957A KR930001467B1 (en) 1990-09-20 1990-09-20 Apparatus for dvp

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900014957A KR930001467B1 (en) 1990-09-20 1990-09-20 Apparatus for dvp

Publications (2)

Publication Number Publication Date
KR920006834A true KR920006834A (en) 1992-04-28
KR930001467B1 KR930001467B1 (en) 1993-02-27

Family

ID=19303864

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014957A KR930001467B1 (en) 1990-09-20 1990-09-20 Apparatus for dvp

Country Status (1)

Country Link
KR (1) KR930001467B1 (en)

Also Published As

Publication number Publication date
KR930001467B1 (en) 1993-02-27

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