KR920006434Y1 - Signal detecting circuit for inverter - Google Patents
Signal detecting circuit for inverter Download PDFInfo
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- KR920006434Y1 KR920006434Y1 KR2019900011136U KR900011136U KR920006434Y1 KR 920006434 Y1 KR920006434 Y1 KR 920006434Y1 KR 2019900011136 U KR2019900011136 U KR 2019900011136U KR 900011136 U KR900011136 U KR 900011136U KR 920006434 Y1 KR920006434 Y1 KR 920006434Y1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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Abstract
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Description
제1도는 종래의 전류억제 보호 회로도.1 is a conventional current suppression protection circuit diagram.
제2도는 본 고안의 상전류 억제보호 신호 검출 회로도.2 is a phase current suppression protection signal detection circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 과전류 트립 및 억제신호발생부 11 : U상과전류 억제신호발생부1: Overcurrent trip and suppression signal generator 11: U phase overcurrent suppression signal generator
12 : V상과전류 억제신호발생부 13 : W상고전류 억제신호발생부12: V phase over current suppression signal generator 13: W phase high current suppression signal generator
A1, A11-A14 : 연산증폭기 Iu, Iv, Iw : U, V, W상전류A1, A11-A14: Operational Amplifiers Iu, Iv, Iw: U, V, W Phase Current
D101-D117 : 다이오드 R101-R107 : 저항D101-D117: Diode R101-R107: Resistance
A2, A21, A3 : 비교기 CT1-CT3 : 전류트랜지스터A2, A21, A3: Comparator CT1-CT3: Current Transistor
PC1, PC2, PC11 : 포토커플러PC1, PC2, PC11: Photocoupler
본 고안은 인버터의 과전류 억제보호회로에 관한 것으로, 특히 대전력용기기에 적당하도록한 인버커의 상전류 억제 보호신호 검출회로에 관한 것이다.The present invention relates to an overcurrent suppression protection circuit of an inverter, and more particularly, to a phase current suppression protection signal detection circuit of an inverter adapted to be suitable for high power equipment.
일반적으로 인버터에서는 고전압 대전류를 취급하므로 파워소자의 간격이 높아 과전압 과전류로부터 소지들의 파손을 막는 방법이 강구되어 왔다.In general, since an inverter handles a high voltage and a large current, a method of preventing breakage of materials from overvoltage overcurrent due to a large distance between power devices has been devised.
따라서 존재에는 과전류 검출방법중 전류트랜스 포대를 이용 3상 출력전류를 센싱하여 과전류 억제보호에 사용되고 있는 것으로, 제1도에 도시한 바와같이, 상전류(Iu,Iv,Iw)는 전류 트랜스포머(CT1,CT2,CT3)로 검출하여 다이오드(D1-D6)를 통해 입력 전파 정류되고, 저항(R1)을 병렬 연결하여 정류된 전류의 전압변환용으로 사용하며, 상기 저항(R1)은 볼티지플로워(Voltage fallower)용 연산증폭기(A1)의 비반전(+)측에 연결되어 구성된다. 그리고 연산증폭기(A1)의 출력단은 비교기(A2,A3)의 반전(-)측에 연결되어 기준전압(VOCTREF, VOCREF)과 비교되며, 상기 비교기(A2)는 저항(R2)를 통해 포토커플러(PC1)에 연결되고, 포터커플러(PC1)는 분리용으로 사용되며 그의 2차측 저항(R4), 콘덴서(C1)의 필터를 통해 과전류트립 신호를 출력하며, 상기 비교기(A3)의 후단은 저항(R5-R7), 포토커플러(PC2), 콘덴서(C2)를 통해 상기 비교기 (A2)의 후단과 같이 구성되어 과전류 억제 신호를 출력하게 과전류 트립 및 억제신호발생부(1)로 구성된다.Therefore, in the presence of the overcurrent detection method, the three-phase output current is sensed by using a current transformer bag to be used for overcurrent suppression protection. As shown in FIG. 1, the phase currents Iu, Iv, and Iw are current transformers CT1, It is detected by CT2 and CT3 and rectified by full-wave input through diodes D1-D6, and used for voltage conversion of rectified current by connecting resistors R1 in parallel. The resistor R1 is a voltage follower. It is connected to the non-inverting (+) side of the operational amplifier (A1) for fallower). The output terminal of the operational amplifier A1 is connected to the inverting (-) side of the comparators A2 and A3 to be compared with the reference voltages VOCCTREF and VOCREF, and the comparator A2 is connected to the photocoupler through the resistor R2. PC1), the port coupler PC1 is used for separation and outputs an overcurrent trip signal through a filter of the secondary resistor R4 and the capacitor C1, and the rear end of the comparator A3 is a resistor ( R5-R7, the photocoupler PC2, and the capacitor C2 are configured as the rear end of the comparator A2, and constitute the overcurrent trip and suppression signal generator 1 to output the overcurrent suppression signal.
이와같이 구성된 종래의 전류억제 보호회로는 U, V, W상전류(Iu,Iv,Iw)가 전류 트랜스포머(CT1-CT3)를 통해 2차측으로 넘어오며, 이의 전류는 다이오드(D1-D6)를 통해 2차측으로 넘어오면, 이의 전류는 다이오드(D1-D6)를 통해 전파정류된다. 이와같이 전파정류된 전류는 저항(R1)으로 흐르게 되어 전압을 형성한 후볼티지 플로워용 연산증폭기(A1)을 통해 비교기(A2,A3)의 반전(-)측에 입력되어 과전류트립 기준전압(VOCTREF), 과전류억제 기준전압(VOCREF)과 비교된다.In the conventional current suppression protection circuit configured as described above, U, V, and W phase currents (Iu, Iv, Iw) are transferred to the secondary side through the current transformers (CT1-CT3), and the current thereof is passed through the diodes (D1-D6). On the other side, its current is full-wave rectified through the diodes D1-D6. The full-wave rectified current flows through the resistor R1 to form a voltage, and is input to the inverting (-) side of the comparators A2 and A3 through the voltage follower operational amplifier A1, and the overcurrent trip reference voltage (VOCTREF). This is compared with the overcurrent suppression reference voltage (VOCREF).
여기서 과전류 트립 기준전압(VOCTREF)이 반전(-)측의 입력전압보다 적게 되면 포토커플러(PC1)의 온되고, 크게되면 포토커플러(PC1)가 오프되므로 필터링용 저항(R4), 콘덴서(C1)를 통해 과전류 트립신호로 출력된다. 한편 과전류 억제기준전압(VOCREF)이 반전(-)측의 입력전압보다 작게 되면 포토커플러(PC2)가 온되고, 크게 되면 포토커플러(PC2)가 오프되므로 필터링용 저항(R7), 콘덴서(C2)를 통해 과전류·억제신호로 출력된다.Here, when the overcurrent trip reference voltage VOCCTREF is less than the input voltage on the inverting (-) side, the photocoupler PC1 is turned on, and when the overcurrent trip reference voltage VOCCTREF is larger, the photocoupler PC1 is turned off, so that the filtering resistor R4 and the capacitor C1 are turned off. It is outputted as an overcurrent trip signal. On the other hand, when the overcurrent suppression reference voltage VOCREF becomes smaller than the input voltage on the inverting (-) side, the photocoupler PC2 is turned on, and when the overcurrent suppression reference voltage VOCREF is larger, the photocoupler PC2 is turned off, so that the filtering resistor R7 and the capacitor C2 are It is outputted as an overcurrent suppression signal.
이때 과전류 트립 기준전류(VOCTREF)는 과전류 억제기준전압(VOCREF)보다 크며 최종 출력신호는 저전위 상태가 과전류를 나타내게 된다.At this time, the overcurrent trip reference current VOCCTREF is greater than the overcurrent suppression reference voltage VOCREF, and the low output state of the final output signal indicates the overcurrent.
그런데 상기와 같은 종래의 과전류 검출회로에 있어서는 3상 폴브리지 정류기에서 3상 전류의 피크치만이 검출되어 각상의 전류특성이 무시되므로 검출 신호의 특성을 파악하여 콘트롤하는데 어려움이 있게 되는 문제점이 있었다.However, in the conventional overcurrent detection circuit as described above, since only the peak value of the three-phase current is detected by the three-phase pole rectifier, the current characteristics of each phase are ignored, which makes it difficult to grasp and control the characteristics of the detection signal.
본 고안의 목적은 각상 전류를 분리하여 개별적 억제신호를 내어줌으로써 기준회로의 특성을 갖게 함은 물론 각상 전류의 특성이 무시되는 것을 해소하도록한 인버터의 상전류 억제보호 신호검출회로를 안출한 것으로, 이하 첨부한 도면에 의해 상세히 설명한다.The purpose of the present invention is to provide a phase current suppression protection signal detection circuit of an inverter that separates each phase current to give a separate suppression signal to provide the characteristics of the reference circuit as well as to eliminate the neglect of the characteristics of each phase current. It demonstrates in detail by an accompanying drawing.
제2도는 본 고안의 상전류 억제 보호신호 검출회로로서 이에 도시한 바와같이, U상전류(Iu)는 전류 트랜스포머(CT1)를 통해 브리지 다이오드(D101-D104)에 접속되어 있어 저항(R1)에 전류정류된 전류를 공급하며, 저항(R101)은 연산증폭기(A11)에 전압을 공급하여 비교기(A21)로 출력한다. 여기서 비교기(A21)의 비반전(+)측과 출력단자에 저항(R4), 다이오드(D117)를 연결하여 히스테리시스(hysterisis)를 주고 저항(R105)을 통해 포토커플러(PC11)에 연결하여 전원을 분리하고, 저항(R107), 콘덴서(C1)를 통해 노이즈성 신호를 필터링하여 U상과전류 억제신호를 출력하게 U상과전류 억제신호발생부(11)를 구성한다.2 is a phase current suppression protection signal detection circuit of the present invention, as shown here, the U phase current (Iu) is connected to the bridge diode (D101-D104) through the current transformer (CT1) to rectify the current to the resistor (R1) The supplied current is supplied, and the resistor R101 supplies a voltage to the operational amplifier A11 and outputs it to the comparator A21. Here, the resistor R4 and the diode D117 are connected to the non-inverting (+) side and the output terminal of the comparator A21 to give hysteresis and connected to the photocoupler PC11 through the resistor R105 to supply power. Separately, the U phase overcurrent suppression signal generator 11 is configured to filter the noise signal through the resistor R107 and the condenser C1 to output the U phase overcurrent suppression signal.
또한 V상전류(Iv)는 전류 트랜스포머(CT2)를 통해 브리지 다이오드(D5-D8)에 접속되어 있어 저항(R2)에 전파정류된 전류를 공급한 후 연산증폭기(A12)를 통해 전압을 공급하고, 상기 U상과전류 억제신호발생부(11)와 같은 구성으로 V상과전류 억제신호를 출력하게 V상과전류 억제신호발생부(12)를 구성한다.In addition, the V phase current Iv is connected to the bridge diodes D5-D8 through the current transformer CT2 to supply the full-wave rectified current to the resistor R2, and then supply a voltage through the operational amplifier A12. The V-phase overcurrent suppression signal generator 12 is configured to output the V-phase overcurrent suppression signal in the same configuration as the U-phase overcurrent suppression signal generator 11.
그리고 W상전류(Iw)는 전류트랜스포머(CT3)를 통해 브리지 다이오드(D109-D112)에 접속되어 있어 저항(R103)에 전파 정류된 전류를 공급한 후 연산증폭기(A13)를 통해 전압을 공급하고, 상기 U상과전류 억제신호발생부(11)와 같은 구성으르 W상과전류 억제신호를 출력하게 W상과전류억제 신호발생부(13)를 구성한다.The W phase current Iw is connected to the bridge diodes D109-D112 through the current transformer CT3 to supply the full-wave rectified current to the resistor R103, and then supply a voltage through the operational amplifier A13. The W-phase overcurrent suppression signal generator 13 is configured to output the W-phase overcurrent suppression signal in the same configuration as the U-phase overcurrent suppression signal generator 11.
한편, 연산증폭기 (A11-A13) 의 출력측(ⓐ-ⓒ)은 각각의 다이오드(D113-D115) 를 통해 연산증폭기 (A14)의 비반전(+)측에 접속하며 상기 연산증폭기(A14)의 반전(-)측 및 출력축에 다이오드(D116)를 접속하여 전압강하를 보상하고, 상기 과전류 트립 및 억제신호발생부(1)를 통해 과전류트립신호 및 과전류 억제신호를 출력하게 구성한다.On the other hand, the output sides ⓐ-ⓒ of the operational amplifiers A11-A13 are connected to the non-inverting (+) side of the operational amplifier A14 through respective diodes D113-D115, and the inverting of the operational amplifier A14 is performed. The diode D116 is connected to the negative side and the output shaft to compensate for the voltage drop, and output the overcurrent trip signal and the overcurrent suppression signal through the overcurrent trip and suppression signal generator 1.
이하, 상기와 같이 구성된 본 고안의 작용효과를 설명한다.Hereinafter, the effect of the present invention configured as described above.
U상전류(Iu)는 전류트랜스포머(CT1)에서 검출하여 다이오드(D101-D104)를 통해 정류된 후 저항(R101)에 전압치로 인가되며, 이의 전압은 연산증폭기(A11)를 통해 비교기(A21)에 입력되어 과전류 억제 기준전압(VOCREF)과 비교된다.The U-phase current Iu is detected by the current transformer CT1, rectified through the diodes D101-D104, and applied to the resistor R101 as a voltage value, and the voltage thereof is supplied to the comparator A21 through the operational amplifier A11. It is input and compared with the overcurrent suppression reference voltage VOCREF.
이때 입력전압이 과전류억제 기준전압(VOCREF)보다 클때 포토커플러(PC1)가 구동되어 저전위로 되는 U상과전류 억제신호가 발생되고, 저항(R4), 다이오드(D117)는 비교기(A21)의 출력레벨이 저전위로 되면 기준전압(VOCREF)을 낮추게 되는 히스테리시스 기능을 수행한다. 여기서 기준전압(VOCREF)을 낮추는 이유는 과전류 억제해제를 최초억제 레벨보다 더낮은 영역에서 시키기 위해주는 히스테리시스치로서 이는 동작의 안전성을 확보하기 위한 것이다.At this time, when the input voltage is greater than the overcurrent suppression reference voltage VOCREF, the photocoupler PC1 is driven to generate a U-phase overcurrent suppression signal having a low potential, and the resistors R4 and D117 are output levels of the comparator A21. This low potential performs a hysteresis function that lowers the reference voltage VOCREF. The reason for lowering the reference voltage (VOCREF) is a hysteresis value for causing the overcurrent suppression to be lower than the initial suppression level. This is to ensure the safety of operation.
한편, 포토커플러(PC1)는 파워와 콘트롤부를 격리시키기 위한 것이고, 저항(R107), 콘덴서(C101)는 노이즈성의 신호를 제거하여 정확한 U상과전류 억제신호를 출력하기 위함이다.On the other hand, the photocoupler PC1 is for isolating the power and the control unit, and the resistor R107 and the capacitor C101 are for removing the noisy signal and outputting the correct U-phase overcurrent suppression signal.
상기와 같이 하여 V상전류(Iv), W상전류(Iw)로 각각 상기 U상과 동일한 회로를 통하여 V상억제신호, W상억제신호를 발생시킨다.As described above, the V phase suppression signal and the W phase suppression signal are generated as the V phase current Iv and the W phase current Iw through the same circuit as the U phase.
그리고 연산증폭기(A11-A13)의 출력측(ⓐ-ⓒ)인 U,V,W상 전류의 전압 변환치는 다이오드(D113-D115)에서 세전압중 가장 큰 전압치의 다이오드만 온되어 접점(ⓓ)에 나타나며, 이의 전압은 접점(ⓐ-ⓒ)전압의 다이오드 전압강하치를 뺀 전압으로 나타나므로 연산증폭기(A14)에 부가된 다이오드(D116)로 다이오드 전압강하로 보상해준다.The voltage conversion values of the U, V, and W phase currents of the operational amplifiers A11-A13, ⓐ-ⓒ, are turned on only at the diodes D113-D115 with only the diode having the largest voltage value among the three voltages. Since the voltage is represented by the voltage minus the diode voltage drop of the contact point (ⓐ-ⓒ) voltage, the diode D116 added to the operational amplifier A14 compensates for the diode voltage drop.
이와같이 하여 보상된 전압은 제1도에서 설명한 바와같이, 비교기(A2)를 통해 과전류 트립기준전압(VOCTREF)보다 크게 되면 포토커플러(PC1)가 구동되어 저전위 상태로 되는 과전류 트립신호를 발생시킨다.As described above, when the compensated voltage is greater than the overcurrent trip reference voltage VOCCTREF through the comparator A2, the photocoupler PC1 is driven to generate an overcurrent trip signal that becomes low.
한편 입력전압은 비교기(A3)를 통해 과전류 억제기준전압(VOCREF)과 비교되며, 이의 전압이 기준전압(VOCREF)보다 크게될때 포토커플러(PC2)가 구성되어 저전위 상태로 되는 과전류 억제신호를 발생시킨다. 여기서 과전류억제 기준전압(VOCREF)이 과전류 트립 기준전압(VOCTREF)보다 낮은 전압치이다.On the other hand, the input voltage is compared with the overcurrent suppression reference voltage VOCREF through the comparator A3, and when the voltage thereof becomes larger than the reference voltage VOCREF, the photocoupler PC2 is configured to generate an overcurrent suppression signal that becomes low potential. Let's do it. Here, the overcurrent suppression reference voltage VOCREF is lower than the overcurrent trip reference voltage VOCCTREF.
이상에서 상세히 설명한 바와같이 본 고안은 3상의 전류상태를 점검할 수 있어 지락사고를 검출할 수 있고 과전류되는 상을 콘트롤할 수 있게 되므로 기존의 회로보다 원인규명이 쉽고 적절하게 대응할 수 있는 효과가 있다.As described in detail above, the present invention can check the current state of three phases, detect a ground fault, and control an overcurrent phase, so that the cause can be easily and appropriately responded to conventional circuits. .
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019900011136U KR920006434Y1 (en) | 1990-07-27 | 1990-07-27 | Signal detecting circuit for inverter |
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| Application Number | Priority Date | Filing Date | Title |
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| KR2019900011136U KR920006434Y1 (en) | 1990-07-27 | 1990-07-27 | Signal detecting circuit for inverter |
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| Publication Number | Publication Date |
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| KR920006434Y1 true KR920006434Y1 (en) | 1992-09-17 |
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