KR920006059Y1 - Automatic white balance control circuit - Google Patents

Abstract

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Description

Automatic White Balance Level Comparison Detection Circuit

1 is an automatic white balance block diagram.

2 is a conventional circuit diagram.

3 is a circuit diagram of one embodiment of the present invention.

(A) of FIG. 4 is a conventional voltage regulation gain amplifier amplification characteristic diagram, (b) is the voltage regulation gain amplifier amplification characteristic diagram of this invention.

* Explanation of symbols for main parts of the drawings

1,1 ': voltage adjustment gain amplifier 3,3': level comparison detector

4,4 ': Up / Down Counter 5,5': Digital / Analog Converter

6,6 ': buffer CP1, CP2: comparator

Q1, Q2, Q3: Transistor OP1, OP2: Op amp

R1... R15: resistor C1-C5: capacitor

The present invention compares and detects the red and blue components of a subject when shooting a video camera, and adjusts the gain of the voltage adjustment gain amplifier to automatically process red (R) and blue (B) signal components at a constant ratio. A balance level comparison detection circuit is provided.

In video cameras, when the subject is photographed using video cameras, the white balance system includes a ratio of R component (long wavelength component in visible light) and B component (short wavelength component in visible light) according to the light source conditions of the subject. In order to prevent red and blue images from appearing differently, the ratio of red and blue signal amplifiers is adjusted by comparing the red and blue signal components so that the ratio is always constant regardless of the light source (a ratio defined by the television signal). Is a system that maintains

In such a white balance system, in order to reduce errors caused by level determination by comparing the color difference signals of (R-Y) and (B-Y) with a reference voltage, in the present invention, (R-Y) and (B-Y) ) And (R-Y) + (B-Y) are compared with the reference voltage to determine the level.

This invention is described in detail based on the accompanying drawings as follows.

First, in white balance, white refers to a color in which RGB, the three primary colors of light, are mixed in the same ratio. The luminance signal of the video signal is composed of Y = 0.3R + 0.59G + 0.11B. The color difference signal components of R-Y and B-Y with respect to 0 become zero. (R-Y = 0, B-Y = 0)

This general white balance adjustment operation will be described based on FIG.

After the R and B inputs are through the voltage-adjusting gain amplifier (1) (1 '), after generating the R-Y and B-Y signals through the R-Y matrix (2) and B-Y matrix (2') This is applied to the level comparison detector 3 (3 ') to compare the levels of R-Y and B-Y.

That is, the level comparison detector 3 (3 ') uses R-Y = 0 and B-Y = 0 in the case of white (the luminance signal of the video signal is composed of Y = 0.3R + 0.59G + 0.11B). ) The levels of R-Y and B-Y are compared.

At this time, if the result of the level comparison detector (3) (3 ') is R-Y <0, or B-Y 0, the output of the level comparison detector (3) (3') becomes a high level and the up / down counter (4) 4 ') is operated as a counter to increase the output voltage of the digital / analog converter 5, 5', which converts the output of the up / down counters 4 and 4 'into an analog voltage.

The output of the digital-to-analog converter 5, 5 'is connected to the voltage adjusting gain amplifier 1', which is an R signal amplifier, and the voltage adjusting gain amplifier 1 ', which is a B signal amplifier, through the buffers 6, 6'. The gain of the R and B signals is increased by being applied to the gain control terminal CR (CB).

In addition, the R-Y and B-Y signals whose gains are increased in the voltage adjusting gain amplifier 1 (1 ') are applied to the level comparison detector (3) (3') again to be compared with the reference voltage. The white balance was adjusted automatically by repeating the operation until Y = 0 and B-Y = 0 (white).

At this time, the characteristic that the amplification degree (gain) is changed according to the voltage applied to the gain control terminal (CR) (CB) of the voltage adjusting gain amplifier (1) (1 ') is as shown in (a) of FIG. The gain increases as the terminal CR (CB) voltage increases.

On the contrary to the above, when the level comparison detector 3 (3 ') detects R-Y> 0 and B-Y> 0, the output of the level comparison detector 3 (3') becomes low level, By operating the down / down counters 4 and 4 'as the down counter, the analog voltages of the digital / analog converter 5 and 5' are lowered and the voltage regulating gain amplifier 1 through the buffers 6 and 6 '. The gain control terminal CR (CB) voltage applied to (1 ') is lowered.

Therefore, the R-Y and B-Y signals whose gains are lowered are applied again to the level comparison detector (3) (3 ') to be compared and repeated until R-Y = 0 and B-Y = 0. This will adjust the white balance.

At this time, a signal in which the white balance is adjusted in the R-Y matrix 2 and the B-Y matrix 2 'is output as a composite video signal through the encoder 7 together with the Y signal.

In the white balance adjustment of such a general operation, the level comparison detector 3 (3 ') will be described in detail by comparing the conventional circuit configuration with the circuit configuration of the present invention.

The conventional level comparison detector compares the R-Y and B-Y signals with the reference voltage set by the resistors R6 and R7 as shown in FIG. However, the level comparison detector of the present invention compares (R-Y) and (B-Y) without comparing the R-Y and B-Y signals with the reference voltage as shown in FIG. By determining the level by comparing the reference voltage set by the (+)-(B-Y) and the resistors (R10-R12), an error does not occur and an accurate white balance can be adjusted.

First, the conventional R-Y signal processing will be described based on FIG. 2 which is a conventional circuit diagram.

The R-Y signal input is clamped to the V _R voltage applied to the emitter by a clamp pulse applied to the transistor Q1 to the collector.

That is, the R-Y signal is clamped to the clamp pulse and the V _R voltage by driving the transistor Q1, and then converted into a current voltage by the integrating circuit of the resistor R3 and the capacitor C3, and then the inverting terminal of the comparator CP1. It is applied to (-).

At this time, the non-inverting terminal (+) of the comparator CP1 is connected to the reference voltage (R6) by R7. Is applied, the comparator CP1 compares both inputs and outputs a high level when R-Y <0, and outputs a low level when R-Y> 0.

In this way, the level comparison detector 3 compares the R-Y signal with a reference voltage so that a greater than and less than the comparison voltage is detected by the comparator CP1, and then the up / down counter 4 outputs a clock signal to the output of the comparator CP1. By up counting or down counting, the output voltage of the digital-to-analog converter 5 also changes.

In other words, when R-Y>, the comparator CP1 outputs a low level, the up / down counter 4 operates as a down counter so that the output voltage of the digital-to-analog converter 5 is also reduced and R-Y <0. CP1 outputs a high level and the up / down counter 4 operates as an up counter to increase the output voltage of the digital / analog converter 5.

The output voltage of the digital-to-analog converter 5 is applied to the gain control terminal CR of the voltage adjustment gain amplifier 1 shown in FIG. 1 after passing through the buffer 6, thereby being a voltage adjustment gain amplifier which is an R signal amplifier. The gain of (1) is raised and lowered.

That is, the above process is repeated so that R-Y input signal levels are compared and detected so that R-Y = 0.

At this time, the gain characteristic diagram of the voltage adjusting gain amplifier 1 is as shown in (a) of FIG.

In the same manner as the above R-Y signal processing, the B-Y signal is also processed to adjust B-Y = 0.

As described above, conventionally, an error between the signals is generated by comparing the R-Y and B-Y signals with reference voltages to detect the level comparison.

In order to solve such a problem, the present invention compares (R-Y), (B-Y), (R-Y) + (B-Y) with a reference voltage to determine the level comparison detector. It was configured as in.

In other words, the present invention clamps the (R-Y) and (B-Y) signals inputted through the voltage adjusting gain amplifiers (1) (1 ') and the matrix (2) (2') to detect and compare with the reference voltage. The output of the comparison detector 3, 3 'controls the counting operation of the up / down counter 4, 4' and the output of the up / down counter 4, 4 'is a digital to analog converter 5 (R-Y) and (B-) applied in the matrix (2) (2 ') in the white balance adjustment for adjusting the gain of the voltage adjustment gain amplifier (1) (1') through (5 '). Y) Compare the level difference between the signals and connect the up / down counters 4 and 4 'with the output comparing the ((R-Y) + (B-Y)) signal with the reference voltage to control the level comparison detector. (3) (3 '), and the comparison outputs of the (R-Y) and (B-Y) signals of the level comparison detectors (3) and (3') include an up / down counter (4) and a digital / analog converter. Voltage adjustment gain amplifier (1 ') through op amp (OP1) and OP2 through (5) (R-Y) + (B-Y) signal and the reference output are compared with the up / down counter (4) (4 ') and the digital / analog converter (5'). Through the op amp OP2, the gain of the voltage regulating gain amplifier 1 'is adjusted to be adjusted to configure the buffer parts 6 and 6'.

Here, the level comparison detectors (3) and (3 ') are (R-Y) and (B-Y) signal-rule resistors (R3) (R4) and capacitors (C3) (C4) clamped to the V _R voltage by a clamp pulse. And a transistor (Q3) for combining the (R-Y) and (B-Y) signals and integrating the signals (R-Y). Comprising a comparator (CP2) for comparing + (B-Y) with a set reference voltage, and to control the count operation of the up / down counter (4) (4 ') to the output of the comparator (CP1) (CP2) Configure the connection.

In the present invention of such a configuration, the R-Y signal is clamped to the V _R voltage through the transistor Q1 to which the clamp pulse is applied, and the R-Y signal is also coupled to the V _Q voltage of the transistor Q2 to which the clamp pulse is applied. To be clamped.

The R-Y and B-Y signals clamped by the transistors Q1 and Q2 are converted to DC levels through the resistors R3 and R4 and the capacitor C3 and C4, and then the comparator CP1 The R-Y signal is applied to the inverting terminal (-) and the B-Y signal is applied to the non-inverting terminal (+) for comparison.

Therefore, the comparator CO1 compares R-Y and B-Y and outputs a low level when R-Y> B-Y and outputs a high level when R-Y> B-Y. By controlling the output of), the voltage output from the digital-to-analog converter 5 is also controlled.

That is, the output of the comparator CP1 at R-Y> B-Y outputs a low level and the high level at R-Y <B-Y. The counter adjusts the output voltage of the digital-to-analog converter 5 by the former, and the latter by increasing the voltage through the buffers 6 and 7, and then adjusts the gain control terminal CR of the voltage-adjusting gain amplifier 1 and 1 '. (CB) to reduce the R level by decreasing the amplification degree in the case of the former in the voltage adjusting gain amplifier (1) and to bring the B level to the amplified rising in the voltage adjusting gain amplifier (1 '). do.

In other words, the level comparison detecting section 3 detects the gain of the voltage adjusting gain amplifier 1 (1 ') so that (R-Y) = (B-Y).

At this time, it is shown in FIG. 4B that the amplification degree is changed by the voltage applied to the gain adjusting terminal CR (CB) of the voltage adjusting gain amplifier 1 (1 ').

That is, when the gain adjusting terminal CR voltage rises, the gain of the voltage adjusting gain amplifier 1 increases (A in FIG. 4B), and when the gain control terminal CB voltage increases, the voltage adjusting gain amplifier ( The gain of 1 ') is reduced ((B) in FIG. 4 (b)).

In the non-inverting terminal (+) of the comparator CP2, the R-Y and B-Y signals clamped by the transistors Q1 and Q2 are synthesized through the transistor Q3, and then ((R-Y), (B -Y)) The integrated voltage is applied to the DC voltage through the resistor R9 and the capacitor C5, and the reference voltage of the resistors R10-R12 is extended to the inverting terminal (-) of the comparator CP2.

Therefore, the comparator CP2 outputs a high level when ((R-Y) + (B-Y))> 0 and a low level when ((R-Y) + (B-Y)) <0. Through the up / down counter 4 'and the digital / analog converter 5', the voltage rises in the former and decreases in the latter, and the output voltage of the digital / analog converter 5 'is buffered (6). After ') is applied to the gain control terminal (CB) of the voltage adjustment gain amplifier (1').

Therefore, if ((R-Y) + (B-Y))> 0, reduce the B level, and if ((R-Y) +, (B-Y) <0, increase the R level and then raise the level again. By repeating the operation applied to the comparison detector 3 ', (R-Y) + (B-Y) = 0, the white balance is adjusted.

At this time, the output of the digital-to-analog converter 5 is simultaneously applied to the op amps OP1 and OP2, which are the buffers 6 and 6 ', so that the voltage adjusting gain amplifier 1 and 1' shown in FIG. It was adjusted at the same time and the output of the digital / analog converter 5 'was applied only to the op amp OP2 to adjust the gain of the voltage regulating gain amplifier 1'.

As described above, the present invention controls the red signal amplifier and the blue signal amplifier at the same time, so that the adjustment speed of the correct white balance is increased and is generated when the conventional (R-Y) and (B-Y) signals are detected in comparison with the reference voltage. The error can be reduced by comparison between each signal ((R-Y) and (B-Y)) and by comparing the reference voltage with the signal ((R-Y) + (B-Y)) mixed with each signal. It works.

That is, compared to the conventional level comparison detector, the occurrence of error is significantly reduced by comparing each signal, comparing each signal mixed with the reference voltage, and controlling the red and blue signal amplifiers simultaneously, thereby reducing the white balance adjustment time. It works.

Claims (2)

A level comparison detector (3) which clamps the (R-Y) and (B-Y) signals input through the voltage adjusting gain amplifier 1 (1 ') and the matrix (2) (2') and compares them with the reference voltage (3). 3 'output controls the counting operation of the up / down counter 4 and 4' and the output of the up / down counter 4 and 4 'is a digital to analog converter 5 and 5'. In the white balance adjustment for adjusting the gain of the voltage adjustment gain amplifier (1) (1 ') by means of the (R-Y) and (B-Y) signals applied from the matrix (2) (2'). Compare the level difference and connect the up / down counter (4) and (4 ') to the output comparing the ((R-Y) + (B-Y)) signal with the reference voltage to control the level comparison detector (3) ( 3 '), and the comparison output of the (R-Y) and (B-Y) signals of the level comparison detector 3 (3') provides an up / down counter (4) and a digital / analog converter (5). Gain of voltage regulation gain amplifier (1) (1 ') through op amp (OP1) (OP2) The output of the comparison between the ((R-Y) + (B-Y)) signal and the reference voltage is made through the up / down counter (4 ') and the digital / analog converter (5'). A level comparison detecting circuit for automatic white balance, characterized in that the buffer section (6) (6 ') is configured by connecting the gain of the voltage adjusting gain amplifier (1') to adjust the gain. 2. The level comparison detector (3) (3 ') is provided with a resistor (R-) and a capacitor (R-) and (B-Y) signals clamped to the voltage V _R by a clamp pulse. And a transistor (Q3) having a comparator (CP1) for integrating and comparing with (C3) and (C4), and for synthesizing the (R-Y) and (B-Y) signals, A comparator CP2 for comparing (R-Y) + (B-Y)) with a set reference voltage, and then outputting the up / down counters 4 and 4 'to the output of the comparator CP1 and CP2. Automatic white balance level comparison detection circuit configured to control the count operation.