KR920004975A - Interface circuit of AT-bus and I / O controller processor using dual port RAM - Google Patents

Abstract

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Description

Interface circuit of AT-bus and I / O controller processor using dual port RAM

As this is a public information case, the full text was not included.

1 is a block diagram according to the present invention.

2 is a detailed circuit diagram of the AT-bus interface unit 30 during the first view.

3 is a detailed circuit diagram of the DPR mediation logic section 50 during the first view.

4 is an operation timing diagram of each part of FIG. 2 and FIG.

* Explanation of symbols for main parts of the drawings

10: I / O controller processor 20: buffer

30: AT-bus interface unit 40: DPR

50: DPR arbitration logic section 60: re-flash and DPR control logic section

70: memory decode logic

Claims (3)

In the interface circuit of the AT-bus and the I / O controller processor using a dual port lab, the 32-bit I / O controller processor 10 which controls the I / O controller as a whole, and the address, the control signal, and the data of the I / O controller processor 10 Between the buffered buffer 20, the 16-bit wide AT-bus having an address bus 1100, a control bus 1200, and a data bus 1300, and the input / output controller processor 10 through the buffer 20. An AT-bus interface unit 30 for buffering and controlling data transmission, and having a predetermined memory area and accessed by the host and the input / output controller processor 10 via the AT-bus via a data bus 2300. A bit width DPR 40 and a control bus 2200 control the host and the input / output controller processor 10 to control the DPR 40. A refresh and DPR control logic unit 60 which controls the refresh and access of the DPR 40, which is controlled through the DPR mediation logic unit 50 that arbitrates memory sharing, the address bus 2100, and the control bus 2200. And a memory decode logic unit 70 which decodes the address signal of the input / output controller processor 10 to control the memory mapping of the DPR 40. And the interface circuit of the processor of the I / O controller. 2. The byte enable of claim 1, wherein the AT-bus interface unit 30 distinguishes the lower two-bit addresses SAØ, SA1, and byte and word units among the addresses from the host through the address bus 1100. A byte selection circuit 11 for inputting a signal SBHE to output a first-fourth byte selection signal S1-S4 for selecting an access byte of the DPR 40, and through the address bus 1100. 1-bit address SA1 of the address of the host and its inverted address And a memory selection signal through the control bus 1200 Memory lead signal And lower 8-bit data (D? -D7) and upper 8-bit data (D8-D15) through the data bus 1300 accessed to the DPR 40 and 32-bit data (RD?) Through the data bus 2300. A host enable signal via the control bus 2200 of RD31; Interface circuit of the AT-bus and input / output controller processor using the dual port RAM, characterized in that the buffer control circuit 12 for controlling the buffer object by inputting. The memory selection signal of claim 1, wherein the DPR mediation logic unit 50 comprises the memory selection signal of the host. And a RAM selection signal of the input / output controller processor 10. And system clock (CLK) and its inverted clock And system reset signal Host enable signal that arbitrates access of the DPR 40 by inputting And controller enable signals A DPR access enable circuit 31 and a host enable signal for outputting to the host and the input / output controller processor 10, respectively; And the controller enable signal. And a memory write signal from the host And memory lead signals And a data strobe signal from the input / output controller 10. And a system reset bus signal (RESET) and the inverted clock Input and output channel ready signal to the host Generates and outputs a data strobe activation signal to the input / output controller processor (10). A weight circuit 32 and a system clock CLK to generate a weighted state so that the host and the input / output controller processor 10 can access the DPR 40 at the same time so that the host and the input / output controller processor 10 can access the DPR 40 at the same time. And an logic circuit (N2) provided to the DPR access circuit (31) and the weight circuit (32) by inverting the interface circuit of the AT-bus and the input / output controller processor using the dual port RAM. ※ Note: The disclosure is based on the initial application.