KR920003363B1 - Error correction circuit for digital transmission system using duobinary code - Google Patents

Abstract

The circuit includes a first comparator (1) for extracting signals only when input signals are larger than a reference signal. A second comparator (2) extract signals only when input signals are smaller than a reference signal. A first shift register means consists of D flip-flops (3-6) which generate outputs in accordance with the period of the system clocks. A first gate means includes NAND gates (G2,G3) and an OR gate (G1), and controls the operation of the first shift register. A first switching means is switched by the output signal of the first gate means, and controls the inverted input of the first comparator (1). A second shift register consists of D flip-flops (7-10), and outputs in accordance with the period of the system clocks. The circuit further includes a second gating means and a second switching means.

Description

Error Correction Circuit of Duo Binary System

1 is a circuit diagram of the present invention.

2 is a waveform diagram in normal operation according to the present invention.

3 is a waveform diagram of an error correction process when an error occurs according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 2: 1st, 2nd comparator 3-10: D flip flop

11, 12: 1st, 2nd shift register G1: Oagate

G2, G3, G5, G6: NAND gate G4: Noah gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication system, and more particularly to a circuit applied to a front end of a decoder in a process of transmitting and receiving information in a bipolar PCM transmission system applying a duobinary code. It is about.

In the digital communication system using the current PCM code, it will be time to transmit digital information not only voice information but also image information. However, the transmitted information does not transfer correct information due to noise, frequency characteristics, and phase distortion due to external influences. In other words, due to the development of the transmission system, the transmission speed is increased and the accompanying conditions have to increase the bandwidth of the signal. When the bandwidth of the signal is widened, there is a problem in that a signal error is caused by the noise due to the widening of the signal.

Accordingly, an object of the present invention is to detect and shift whether two pulses exist during one clock cycle when a signal distortion or an error occurs due to external influences during transmission and reception of information of audio information and image signal. An error correction circuit in a duobinary system that can correct at the very beginning of a register is provided.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a circuit diagram of the present invention, in which a first comparator 1 extracts only a signal when a received signal is input and the signal is larger than a reference signal, and a signal is smaller than the reference signal when the received signal is input. The second comparator 2 for extracting only the signal of? And the D flip-flop 3-6 by the number of bits corresponding to the PCM code for inputting and outputting the output signal of the first comparator 1 according to the system clock period. NAND gates G2, G3 and OA gates for controlling the operation of the first shift register means after detecting an error by gating the first shift register means and the input / output signals of the first shift register means. A resistor R1, a variable resistor R2, and a transistor Q1 for controlling the inverting input of the first comparator 1 by switching by a first gate means composed of G1 and an output signal of the first gate means. First consisting of Switching means and second shift register means for configuring the D flip-flop 7-10 by the number of bits corresponding to the PCM code for input by the output signal of the second comparator 2 and output according to the system clock period; A second gate means consisting of NAND gates G5 and G6 and NOR gate G4 for controlling an operation of the second shift register means after detecting an error by gating an input / output signal of the second shift register means; And second switching means including a resistor R3, a variable resistor R4, and a transistor Q2 to control the non-inverting input of the second comparator 2 by switching by an output signal of the second gate means. Configure.

2 is a waveform diagram of normal operation according to the present invention, (a) is a source waveform of a transmission system, (b) is a waveform input upon reception, and (c) is a first reference signal Vr1. This is a waveform obtained by slicing only a signal corresponding to +1 from the first comparator 1, and (d) corresponds to -1 from the second comparator 2 using the second reference signal Vr2. The waveform is obtained by slicing only the signal, (e) is a clock pulse of the system, (f) is a waveform shaped by the first shift register means, and (g) is a waveform shaped by the second shift register means.

3 is a waveform diagram of an error correction process when an error occurs according to the present invention, (b1) is a waveform in which a received signal has an error in a dotted line portion, and (c1) is a slicing by the first reference signal Vr1. Is a waveform, (d1) is a waveform sliced by the second reference signal Vr2, (e1) is a system clock pulse, (f1) is a shaped waveform through the first shift register means, (g1) Is a waveform that has been shaped by the second shift register means, (f2) is a waveform in which the error of the (f1) waveform is corrected, and (h2) is a waveform obtained by adding the (g1) waveform and the (f2) waveform.

Based on the above configuration, the present invention will be described in detail with reference to FIGS. First of all, when comparing binary data and duo binary code, duo binary code transmits the signal's bandwidth in half than that of binary transmission. have.

(C: channel capacity of a given transmission panel, B: bandwidth, S / N: signal-to-noise ratio)

In addition, when the transfer rate is gradually increased, the probability of error increases proportionally, and thus, an excellent code sharpening part is required. Before describing the present invention, the characteristics of the coding process of the bipolar PCM system applying the duo binary code are regular.

The code sequence is mapped in the order of + 1 → 0 → -1 → 0 → + 1 or + 1 → 1 → + 1. And since there can never be two pulses in one clock cycle, if two pulses are present they are detected and corrected at the very beginning of the shift register.

First, when the 2a wave form is transmitted to the input side IN of the receiving end shown in FIG. 1, and the wave is normally received, the 2b wave is also inputted, and external influences such as noise and distortion of the interference are input. In this case, a signal such as the modified third waveform (b1) is input. When the modified signal is input to the first and second comparators 1 and 2, respectively, and the reference voltage Vr1 is input to the inverting terminal to the first comparator 1, the input signal is larger than the reference voltage Vr1. Extract only the signal and output it. In addition, the second comparator 2 receives a reference voltage Vr2 as a non-inverting input terminal and outputs only a signal having a level lower than that of the reference voltage Vr2.

A data stream composed of n bits output from the first and second comparators 1 and 2 is composed of first shift register means composed of D flip-flops 3-6 and D flip flops 7-10. Input to the shift register means. Each of the input positive values is input to a storage element and connected to a decoder. First, in the case of the first comparator 1 processing the positive value, the output of the first comparator 1 has a D flip-flop 3 connected to the input terminal D and the D flip-flop ( 3) constitutes the first shift register means by the number of bits corresponding to the PCM code.

This is not a problem when the input signal of the D flip-flop 3 is LPOW. However, when the input signal of the D flip-flop 3 is high, a high state is output according to a system clock cycle. If two high states are created during one clock cycle, it is a violation of system characteristics and one of the two high pulses should be detected and turned low. According to the constant regularity, if the data waveform goes from low to high, the error of the two high pulses is the previous error. If the data waveform goes from high to low, the error of these two low pulses is forward. Therefore, as shown in FIG. 3 (C1), an error occurs in the process of going up to the second high state. The second pulse is connected to the input of the D flip-flop (3), the clock terminal (CK) is connected to the system clock (SCLK), such as the waveform of Figure 3 (e1), the clear terminal (CLR) is the NAND gate (G2) An output terminal is connected, and the D flip-flop 3 input / output terminals D1 and Q1 are connected to the NAND gate G2 input. Here, if the signals applied to the input and output terminals D1 and Q1 are both high, a low is output to the NAND gate G2, forcing the output of the D flip-flop 3 to be low, and the NAND gate The error message (G2) is input to the oragate G1.

In addition, the D flip-flop 4 and the NAND gate G3 operate in the same manner as the above operation. As the transmission speed of the communication system is fast and the bandwidth is narrowed, the reception frequency tends to increase accordingly. If the gate processing speed and clock cycle are similar, there is a fear that error correction may occur in the D flip-flop 3. Therefore, the NAND gate G3 is also connected to the clear terminal CLR of the D flip-flop 4 to perform correction, thereby reducing the probability of error correction. In addition, the output of the NAND gate G3 is also input to the oragate G1. When the two input signals are low, the oar gate G1 cuts off the level adjusting transistor Q1 to raise the level of the first reference voltage Vr1, thereby increasing the level of the first comparator. 1) can be detected. All operations in the second comparator 2 are the same as those in the first comparator 1, and the second shift register means is the same as the operation of the first shift register means, except that the input of the noah gate g4 is When all are low, the output becomes high, which saturates the level adjusting transistor Q2, so that the level of the second reference voltage VR2 is lowered so that a more accurate low level can be read.

As described above, when the duo binary PCM system fails to deliver correct information due to frequency characteristics or phase distortion due to noise or external interference signal generated in the transmission channel, the correct information can be detected by detecting the error. There is an advantage.

Claims (2)

In a coating sequence circuit of a digital communication system using a PCM code, a first comparator (1) which inputs a received signal and extracts only a signal when the signal is larger than a reference signal, and a received signal is inputted to this signal Is a second comparator 2 for extracting only the signal when the signal is smaller than the reference signal, and the output signal of the first comparator 1 is input and flipped by the number of bits corresponding to the PCM code to output according to the system clock period. NAND gate G2 for controlling the operation of the first shift register means after detecting an error by gating the first shift register means constituting the flop 3-6 and the input / output signal of the first shift register means. A first gate means consisting of G3 and an oragate G1, first switching means for controlling an inverting input of the first comparator 1 by switching by an output signal of the first gate means, Second shift register means for configuring the D flip-flop 7-10 by the number of bits corresponding to the PCM code to be inputted by the output signal of the second comparator 2 and output according to the system clock period, and the second shift register means; A second gate means for controlling the operation of the second shift register means and an output signal of the second gate means and switching the second comparator 2 after detecting an error by gating an input / output signal of the shift register means. And a second switching means for controlling the non-inverting input of the error correction circuit in the duo binary system. The data processing according to claim 1, wherein the data is processed by separating the first and second comparators (1, 2) using the first and second reference signals (Vr1, Vr2) to obtain +1 and -1 values of the duo binary code, respectively. Error correction circuit in a duo binary system.

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