KR920001550A - Nonvolatile semiconductor memory device and data erasing method - Google Patents

Nonvolatile semiconductor memory device and data erasing method Download PDF

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Publication number
KR920001550A
KR920001550A KR1019910009924A KR910009924A KR920001550A KR 920001550 A KR920001550 A KR 920001550A KR 1019910009924 A KR1019910009924 A KR 1019910009924A KR 910009924 A KR910009924 A KR 910009924A KR 920001550 A KR920001550 A KR 920001550A
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South Korea
Prior art keywords
electric
data
memory cells
high voltage
block
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KR1019910009924A
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Korean (ko)
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KR950006212B1 (en
Inventor
야스 데라다
다께 나까야마
신이찌 고바야시
요시와 미야와끼
마사끼 하야시고시
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시기 모리야
미쓰비시뎅끼가부시끼가이샤
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable

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  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

내용 없음No content

Description

불휘발성 반도체기억장치 및 그의 데이타소거방법Nonvolatile semiconductor memory device and data erasing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 하나의 실시예의 후레쉬 EEPROM의 부분개략 블록도,1 is a partial schematic block diagram of a fresh EEPROM in one embodiment of the present invention;

제4도는 본 발명의 다른 실시예의 후레쉬 EEPROM의 구성을 나타내는 부분개략 블록도.4 is a partial schematic block diagram showing the configuration of a fresh EEPROM according to another embodiment of the present invention.

Claims (2)

복수의 메모셀을 지닌 메모리셀어레이를 갖추어 전기 메모리셀어레이는 적어도 제1및 제2의 블록으로 분활되어 전기 메모리셀의 각각은 아바란쉬 붕괴를 이용하여 데이타써넣기를 하여 또한 터널현상을 이용하여 데이타소거를 할수 있는 전개효과 반도체소자를 갖추어 데이타소거모드에 있어서 전기 제1의 블록에 갖추어진 모든 전기 메모리셀에 전기 터널현상이 발생하는데 충분한 고전압을 일괄하여 인가하는 제1의 고압인가수단과, 전기데이타소거 모드에 있어서 전기 제2의 블록에 갖추어진 모든 전기 메모리셀에 전기 터널현상이 발생하는데 충분한 고전압을 일괄하여 인가하는 제2의 고압인가수단과, 전기데이타소거모드에 있어서 전기 제1및 제2의 블록에 갖추어진 전기 메모리셀의 기억데이타를 읽어내는 수단과, 전기 읽어내는 수단에 의해서 읽어낸 데이타에 의거하여 전기 제1및 제2의 고압인가수단을 개별적으로 능동화/불능동화 하는 수단과를 거듭마련한 불휘발성 반도체기억장치.Equipped with a memory cell array having a plurality of memo cells, the electric memory cell array is divided into at least first and second blocks so that each of the electric memory cells writes data using avalanche decay and also uses tunneling. A first high voltage applying means having a semiconductor element capable of erasing data and applying a high voltage sufficient to generate an electric tunnel phenomenon to all electric memory cells equipped in the first block in a data erasing mode in a data erasing mode; Second high voltage applying means for collectively applying a high voltage sufficient to generate an electric tunnel phenomenon to all the electric memory cells provided in the second block in the electric data erasing mode; Means for reading out the memory data of the electric memory cell provided in the second block, and means for reading out the electricity Electrical first and second high-voltage applying means for individually activation / out moving picture nonvolatile semiconductor memory device provided with means for the repeated on the basis of the read data. 복수의 메모리셀을 지닌 메모리셀어레이를 갖추어 전기 메모리셀어레이는 적어도 제1및 제2의 블록으로 분할되어, 전기 메모리셀의 각각은 아바란쉬붕괴를 이용하여 데이타써넣기를 행하여 또 터널현상을 이용하여 데이타제거를 할수가 있다. 전개효과 반도체소자를 갖춘 불휘발성반도체 기록장치의 데이타소거방법이며, 데이타소거 모드에 있어서 전기 제1의 블록에 갖추어진 모든 전기 메모리셀에 전기터널현상이 발생하는데 충분한 고전압을 일괄하여 인가하는 스텝과 전기 소거모드에 있어서 전기 제2의 블록에 포함된 모든전기 메모리셀에 전기터널 현상을 발생케하는데 충분한 고전압을 일괄하여 인가하는 스텝과, 전기 데이타소거모드에 있어서 전기 제1및 제2의 블록에 포함되는 전기메모리셀의 기억데이타를 읽어내는 스텝과, 전기읽어냄으로 읽어낸 데이타에 의거 전기 제1의 블록에 지닌 모든 전기 메모리셀 및 전기 제2의 블록에 지닌 모든 전기 메모리셀에 개별로 동시에 선택적으로 전기터널 현상이 발생하는데 충분한 고전압을 인가하는 스텝과를 갖추어진 불휘발성 반도체기억장치의 데이타소거 방법.A memory cell array having a plurality of memory cells is provided so that the electric memory cell array is divided into at least first and second blocks, and each of the electric memory cells writes data by using abaranche collapse and uses tunnel phenomena. You can remove the data. Development Effect A data erasing method for a nonvolatile semiconductor recording device having a semiconductor element, comprising the steps of applying a high voltage sufficient to generate an electric tunnel phenomenon to all electric memory cells provided in the first block in the data erasing mode; Collectively applying a high voltage sufficient to cause an electric tunnel phenomenon to all the electric memory cells included in the electric second block in the electric erase mode, and to the electric first and second blocks in the electric data erase mode. A step of reading out the memory data of the included electric memory cell, and separately at the same time to all the electric memory cells in the first block and all the electric memory cells in the second block based on the data read by the electric reading Optionally, a nonvolatile semiconductor device equipped with a step for applying a high voltage sufficient to cause an electric tunnel phenomenon. How to erase the data of the device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009924A 1990-06-15 1991-06-15 Non-volatile semiconductor memory device and data erasing method thereof KR950006212B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP15835890 1990-06-15
JP2-158358 1990-06-15
JP90-158358 1990-06-15

Publications (2)

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KR920001550A true KR920001550A (en) 1992-01-30
KR950006212B1 KR950006212B1 (en) 1995-06-12

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