KR920001417B1 - Conference calling system - Google Patents

Abstract

The apparatus provides a means for holding a conference through telephone lines, and the apparatus includes: a level coupling means (1) for converting various commands of a high level to a suitable form; a bidirectional RAM (2) for storing various information of a high level; a central control means (3) for controlling the related circuits; a conference communication means (4) for enabling conference communications under the control of the central control means (3); a testing and information collecting means (5) for performing testing functions and for collecting information after the termination of the conference.

Description

Digital conference call device for electronic exchange

1 is an overall configuration diagram of the present invention.

2 is a block diagram of a high level matching unit.

3 is a diagram showing an address appointment type between a higher level and the apparatus of the present invention.

4 is a left area memory map display diagram of the two-way RAM.

5 is a function control message type display diagram of the device of the present invention.

6 is a block diagram of a central control unit.

7 shows the direction control circuit of the data buffer and its output display.

8 is an input / output signal diagram of a memory control circuit.

9 is a memory map display diagram by the memory control circuit.

10 is an input / output decoder and an input / output display thereof.

11 is a flow chart of the main routine of the apparatus of the present invention.

12 is a flowchart of an interrupt subroutine of the device of the present invention.

13 is a block diagram of a conference call circuit section.

14 is a block diagram of a test circuit of the apparatus of the present invention.

* Explanation of symbols for main parts of the drawings

1: upper level matching unit 2: bidirectional RAM

3: central control unit 4: conference call circuit unit

5: test and alarm circuit 10: differential signal transceiver

11: serial / parallel conversion means of address / mode

12: circuit pack selection means 13: transceiver ready state generator

14: serial / parallel conversion means of received data

15: parallel / serial conversion circuit of transmission data

16: mono select decoder 18: interrupt circuit

50: central processing unit 51: data buffer

52: address buffer 53: control buffer

54: memory control circuit 55: input / output decoder

56: ROM 57: RAM

58: clock generator 59: reset circuit

90: conference call element 91: differential signal driver

92: differential signal receiver 93: synchronization circuit generator

100: test data transmission means 101: test data output means

102: test data receiving means 103: sub highway decoder

104: output control means 105: loopback data output means

106: loopback data input means

The present invention relates to a conference call device that provides a function that allows multiple subscribers to simultaneously talk among various services of an electronic exchange. Particularly, a conference participant can arbitrarily make a conference call from 3 to 6 characters. High-quality conference with flexibility, voice mixing and all control functions configured digitally, high integration, self-diagnosis and alarm functions, and the condition of the device can be tested by external control. A digital conference call device for an electronic exchange which performs a call service function.

In general, the conference call apparatus includes a N-1 addition method, a maximum value control method, a maximum value +1 addition method, and the like according to a voice mixing method. First, the N-1 addition method adds the N-1 participant's voice signal to the rest of the participants except N's own voice, and all participants can speak at the same time. However, when the number of participants increases, it is necessary to attenuate the voice signal level of each participant in order to prevent an overflow due to an increase in the level of the added voice signal, thereby limiting the number of participants. Second, the maximum value control method compares N participant voice signals input for each predetermined frame to determine the participant whose voice level is the maximum, and transmits the voice signal to the remaining participant. Participants who have only one voice signal and have a small input level have a significant drop in the nature of the meeting due to disadvantage, and the noise caused by the replacement of the maximum participant by comparing the voice signals every certain time becomes a problem. Third, the maximum value +1 control method compares the N participant voice signals input every predetermined time to determine the participant having the maximum voice signal level and the second largest participant, and then mixes the voice signals of the two participant to the remaining participants. The second voice signal is sent to the participant with the maximum voice signal level and the maximum voice signal is sent to the participant with the second voice signal level. Although the nature of the conference can be improved as compared to the control method, when the number of participants is small, the nature of the conference is inferior to that of the N-1 addition method, and the configuration of the apparatus under the control of this method is complicated.

As described above, the N-1 addition method has a limit on the number of participants, but if the number of participants is 10 or less, the voice signal level of each participant does not need to be greatly attenuated. -1 addition method is adopted.

In terms of configuration of the conference call device, it can be divided into analog and digital methods. The analog method mainly used in the existing exchange is a method of directly adding an analog signal when the participant's voice is mixed, and the voice of each participant inputted as a pulse coded modulation (PCM) signal in each time slot. After converting the signal into analog signal through D / A (digital to analog) converter, the analog circuit is mixed and level adjusted in the addition circuit and output through A / D (analog to digital) converter. . This method is composed of D / A conversion circuit, A / D conversion circuit, adder circuit, and so on, so that the density is not reduced, and the conference circuit group is decided by fixed type slot method because of the addition circuit configuration. Therefore, it is not a problem to classify three-party call into one group, but if four or more calls are made into one group, if all participants in the designated group do not participate in the conference call, the remaining time slots become idle and the time slot is used. Since the efficiency is low and the voice signal level is fixed, it is impossible to adjust the voice signal level according to the number of participants.

Accordingly, an object of the present invention is to maximize the use efficiency of the channel using the N-1 voice mixing method and the variable time slot method that can arbitrarily join a conference call up to six characters, and to adjust the conference call level by a program and pulse. The present invention provides a digital conference call device that performs a direct digital mixing function on a multi-channel speech signal of an encoding modulation scheme.

In order to achieve the above object, the present invention provides a high level matching means for converting various types of commands of a high level into a suitable form, and stores various information and high level information for mutual communication by being connected to the high level matching means. Bidirectional RAM. A central control means connected to the two-way RAM to interpret a command stored in the two-way RAM to control an associated circuit, and connected to the central control means to perform a conference call function under the control of the central control means. And a test and alarm means connected to the conference call means, and connected to the central control means to perform a test function under the control of the central control means and to collect alarms of the main portion.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an overall configuration diagram of the conference call apparatus of the present invention. In the drawing, reference numeral 1 denotes a high level matching unit, numeral 2 denotes a two-way RAM, numeral 3 denotes a central controller, numeral 4 a conference call circuit, and numeral 5 a test and alarm circuit. The upper level matching unit 1 is responsible for converting various types of commands of the upper level into a form suitable for the apparatus of the present invention, and the bidirectional RAM 2 communicates between the upper level matching unit 1 and the apparatus of the present invention. Various information and high level information are stored.

The central control section 3 interprets the commands stored in the two-way RAM 2 to control the conference call circuit section 4. In addition, the test and alarm circuit section 5 performs a test of the apparatus and collects alarms of the main parts.

2 is a detailed block diagram of a higher level matching unit, in which 10 is a differential signal transmitter and receiver, 10a is a differential signal receiver A, 10b is a differential signal receiver B, and 10c is a differential signal driver A, 10d. ) Is a differential signal driver B, 10e is a high level A selection circuit part, 10f is a high level B selection circuit part, 11 is an address / mode serial / parallel conversion part, and 12 is a circuit. A pack selector (13) is a transmit / receive ready state generator (14) is a received data serial / parallel converter, (15) a transmit data parallel / serial converter, (16) is a mode select decoder, and (17) is a reset Circuit 18 denotes an interrupt circuit and 19 denotes a circuit state indicator.

The differential signal transceiver 10 is a function unit for stably transmitting and receiving a control signal with a higher level control device. The differential signal receiver converts an input signal of a differential level into a transistor-transistor logic (TTL) level. (10a, 10b), a differential signal driver (10c, 10d) for converting the output signal of the TTL level to the differential level, and the selection function of the upper level A and the upper level B, which performs stable control by consisting of redundancy And high level select circuit sections 10e and 10f.

The serial / parallel converter 11 of the address / mode performs a function of changing an address and a mode signal received in a serial form in parallel, and the address / mode signal converted in parallel is a built-in address / mode latch. After latching in the buffer, the address signal is output to the left address terminal of the two-way RAM 2, which has its own address bus and data bus on the left and right sides, which are independently accessible. The mode signal is output to the mode select decoder 16. Here, the address includes information for determining which channel a subscriber to join a conference call is to perform, and this information is used as the left addressing signal of the two-way RAM (2). The signal contains information on which of the four functions to perform the current function, such as data transmission, data reception, reset, and test.

The circuit pack selection unit 12 is a function unit for determining which circuit pack to perform the conference call function among the apparatus of the present invention, which is composed of several circuit packs, and includes three parallel latches latched in an integrated circuit pack selection latch buffer. The address information is compared with three specific signals input from the outside, and a signal for determining a circuit pack having the same comparison result is generated, and the signal is output to the transmission / reception ready state generator 13.

The transmission / reception ready state generator 13 is a function unit for generating a signal informing the higher level that it is ready to transmit or receive data, and is driven and generated by the circuit pack selection signal generated by the circuit pack selection unit 12. The signal is kept low by an 8-bit data length to be transmitted or received and is outputted to a higher level through the differential signal drivers 10c and 10d.

The serial / parallel converter 14 of the received data converts and latches serial data input from a higher level into parallel data. The latched parallel data is connected to the left data bus of the two-way RAM 2. . This data is stored in the two-way RAM 2 and performs various functions of the apparatus of the present invention under the control of the central control unit 3.

The parallel / serial conversion circuit 15 of the transmission data is a function unit for converting parallel data, which is the result of various tests of the apparatus of the present invention, into serial data, and the serialized data is transferred to a higher level through the differential signal drivers 10c and 10d. Is output.

The mode selection decoder 16 is a function unit for analyzing a function to be performed by a higher level. The mode selection decoder 16 has functions of transmitting data, receiving data, resetting the device of the present invention, and checking the status of the device of the present invention. The command signal is output to each circuit unit to be controlled.

The reset circuit 17 operates under the reset function command signal of the mode selection decoder 16 and is responsible for resetting the apparatus. The interrupt circuit unit 18 is a functional unit for informing a high level of interrupts generated for various test results.

3 is a diagram showing an address appointment type between a higher level and the apparatus of the present invention. In the drawing, reference numeral 20 denotes an unused address A13-A15, reference numeral 21 denotes an information address A12 for left address 9 of the two-way RAM 2, and reference numeral 22 denotes a circuit pack selection information address A9- to conduct a conference call. A11, 23 are sub highway information addresses A7-A8, 24 are time slot information addresses A2-A6, and 25 are information addresses A0-A1 for left address 1-0 of the two-way RAM 2; Represent each.

The serial address input at the upper level becomes A0-A15 converted from the serial / parallel conversion section of the address / mode to the parallel address, and among these addresses, A0-A8 and A12 are the left address bus A0 of the RAM 2 in both directions. Is connected to A9. The apparatus of the present invention is connected to a switch net-work of an electronic exchange through 20 PCM subhighways, each of which transmits and receives, and each subhighway is composed of 32 time slots. The apparatus of the present invention consists of five circuit packs, each of which performs a conference call function for four subhighways. This address contains information on which timeslots in the subhighway the subscribers to join the conference call will conduct the conference call.

In the figure, A13-A15 (20) is not used, A12 (21) is connected to the left address 9 of the two-way RAM 2, and A9-A11 (22) has circuit pack selection information and A7-A8 ( 23) has subhighway selection information in the selected circuit pack. In addition, as A2-A6 24 has time slot information in the selected subhighway, the two-way RAM 2 having a capacity of 1 kilobyte (Kbyte) is divided into two parts by A12 (21) and A7-A8 (23). Divided into 4 equal parts and 32 equal parts by A2-A6. The area of bidirectional RAM 2 allocated to 1 subhighway and 1 time slot is 4 bytes, and the upper level can be designated by A0-A1 (25). The two-way RAM 2 is located.

FIG. 4 is a left area memory map display diagram of the two-way RAM 2, and follows the address promise form of FIG. In the figure, reference numeral 30 denotes a reception information area related to a conference call, 000H-1FFH, 31 denotes a flag area 3FDH, and 32 denotes an interrupt area 3FEH-3FFH, where 'H' is a hexadecimal number. It is an indication symbol. In the 000H-1FFH 30 area, 000H-17FH represents subhighway 0, 080H-0FFH represents subhighway 1, 100H-17H represents subhighway 2, and 18OH-1FFH represents 128 bytes allocated to subhighway 3. Each time slot in the subhighway is allocated four bytes. The 3FDH 31 is a flag area. This flag is used to check whether the device of the present invention is ready to receive control information before the higher level sends various control information to the device of the present invention. If it is (00) H, control information can be sent. If (FF) H, it keeps observing if the value of this area is (00) H.

In the interrupt area 32, the 3FEH area is an interrupt area used by the apparatus of the present invention to perform the test and notify the result to the higher level when the higher level requires various tests. An interrupt area used to inform that various control information has been transmitted, and is directly connected to the interrupt terminal of the central control device of the device of the present invention. In this case, the data content of the 3FFH area is 8 bits of A2-A9, which is valid information obtained by shifting the total 10 bits of A0-A9 including the subhighway selection information and the time slot information in the subhighway to the right twice. Writing this data to the 3FFH area of the left side of the two-way RAM 2 enables the right-side interrupt of the two-way RAM 2 and recovers the interrupt by the central processing unit reading the value of this area.

5 is a display diagram in the form of a control message for controlling the function of the apparatus of the present invention in which the function of the present invention is performed by receiving this control message from a higher level. In the figure, reference numeral 41 denotes a three-party call connection control bit, reference numeral 42 denotes a conference call connection control bit, reference numeral 43 denotes a release control bit from a three-party call and a conference call, and reference numeral 44 denotes a conference call state function control bit. (45) represents the self loopback test control bit, (46) represents the loopback test control bit through the switch network, (47) the unused bit, and (48) represents the conference call circuit test control bit through the switch network. When each data bit of this control message is '1', each function is enabled.

This control message is a variable time slot method that controls three-way call, conference call, and teardown functions for each time slot, and can arbitrarily join a conference call within each subhighway, improving the use of time slots. The program can also be level-controlled, with separate control of conferencing and conference calls. In addition, the state-capable test is a test function of the abnormality of the conference call function, the self loopback test is a test to confirm the abnormality of each function in the apparatus of the present invention, and the loopback test through the switch network is the apparatus of the present invention. Is a test for checking whether there is an abnormality in the connection state between the device and an external related device, and the function of the apparatus of the present invention. The test of the conference call circuit unit through the switch network is a function for testing the abnormality of the conference call circuit. Tests can be performed for each major function, enabling easy maintenance and reliable operation.

6 is a detailed block diagram of the central control unit. In the drawing, reference numeral 50 denotes a central processing unit, 51 denotes a data buffer, 52 denotes an address buffer, 53 denotes a control buffer, 54 denotes a memory control circuit, 55 denotes an input / output decoder, and 56 denotes a ROM, 57, RAM, and 59, initialization reset circuit, respectively.

(machine cycle one),

(memory request),

(input/out-put request),

(memory read),

(memory write)]가 제어버퍼(53)에 연결되어 동작된다. 이러한 데이터 버퍼(51), 어드레스 버퍼(52), 및 제어버퍼(53)들의 사용 목적은 각 신호들이 각각에 연결된 소자들을 구동할 수 있도록 해당 신호들에게 충분한 전류를 공급하기 위한 것이며, 중앙처리용 클럭 발생회로(58)로부터 중앙 처리 장치에 2.5MHz의 클럭 신호가 공급되며, 전원 공급 시작시(power on)에 중앙 처리 장치 초기화 신호의 발생과 상위 레벨에 의한 리셋신호를 처리하는 초기화 및 리셋회로(59)에서 발생된 리셋신호가 중앙 처리 장치(50)에 공급되며, 양 방향 RAM(2)의 오른쪽인 RAM에서 발생하는 인터럽트 신호가 중앙 처리 장치(50)에 공급된다. 또한 어드레스 버퍼(52)의 출력인 어드레스 신호 2선과 제어버퍼(53)의 출력

에 의해서 메모리 제어기(54)가 동작하여 ROM(56)과 RAM(57)이 선택되며, 어드레스 버퍼(52)의 출력인 어드레스 신호 4개와 제어버퍼(53) 출력

에 의해서 입출력 디코더(55)가 동작되며, 제어 신호중

등 3개의 신호가 상기 데이터 버퍼(51)의 방향을 결정한다.The central processing unit 50 is an 8-bit general purpose central processing unit. The 8-bit bidirectional data signal D0-D7 is connected to the data buffer 51, and the 16-bit address signal A0-A15 is the address buffer. 5 control signals [

machine cycle one,

(memory request),

(input / out-put request),

(memory read),

(memory write)] is connected to the control buffer 53 and operated. The purpose of using the data buffer 51, the address buffer 52, and the control buffer 53 is to supply sufficient current to the signals so that the signals can drive elements connected to each other. A clock signal of 2.5 MHz is supplied from the clock generation circuit 58 to the central processing unit, and an initialization and reset circuit for processing the generation of the central processing unit initialization signal and the reset signal due to a higher level at the time of power supply start. The reset signal generated at 59 is supplied to the central processing unit 50, and the interrupt signal generated at the RAM which is the right side of the two-way RAM 2 is supplied to the central processing unit 50. In addition, two address signal lines, which are outputs of the address buffer 52, and outputs of the control buffer 53

The memory controller 54 operates to select the ROM 56 and the RAM 57, and outputs four address signals and control buffers 53, which are outputs of the address buffer 52.

Input / output decoder 55 is operated by

Three signals determine the direction of the data buffer 51.

7 shows the direction control circuit of the data buffer 51 and its output. In the figure, reference numeral 60 in FIG. 7A represents a direction control circuit, and FIG. 7B represents an output of the direction control circuit. When the data buffer 51 reads data from the external circuit of the central processing unit 50 to the central processing unit 50, the AND gate output of the direction control circuit 60 becomes low and the data buffer When 51 is operated in a reception state, and the AND gate output is in a high state, the data is in a transmission state in which data is advanced from the central processing unit 50 to an external circuit. The terminal S / R of the data buffer 51 is a transmission / reception control signal input terminal.

제어 신호를 사용하여 ROM(56) 및 RAM(57)의 어드레스를 구분해주며 ROM(56)선택은 제어신호 RD와 ROM 선택신호인

이 모두 로우 상태일때만 가능하며, RAM(57)의 선택은 양 방향 RAM(2)단자중 왼쪽 및 오른쪽이 동시에 억세스되는지를 감시하는 단자 신호중 오른쪽 감시신호 BUSYR(BUSY right)과 RAM 선택신호인

에 의해서 양 방향 RAM(2)의 오른쪽 포트가 선택된다.8 is an input / output signal diagram of the memory control circuit 54 and the upper address signals A14 and A15.

The control signals are used to distinguish the addresses of the ROM 56 and the RAM 57, and the selection of the ROM 56 is a control signal RD and a ROM selection signal.

This is possible only when all of them are in a low state, and the selection of the RAM 57 is performed by selecting the right monitoring signals BUSYR (BUSY right) and RAM selection signals among the terminal signals that monitor whether the left and right of the two-way RAM 2 terminals are simultaneously accessed.

By the way, the right port of the bidirectional RAM 2 is selected.

9 is a diagram showing a memory map by the memory control circuit. In the drawing, reference numeral 70 denotes a ROM region 71 denotes a RAM region, and 72 denotes an unused region. The ROM area 70 is an area for storing the control program as 16 Kbytes of 0000H-3FFFH out of 64 Kbytes that the CPU 50 can directly address, and the RAM area 71 is a bidirectional RAM 2 having 16 Kbytes of 4000H-7FFFH. As the right area of, you can read / write various data necessary for communication with higher level.

가 로우상태,

이 하이상태일 때 A0-A2에 의해서 출력포트가 선택된다. 여기서, 포트 0-3은 서브하이웨이 0-3에 대한 각각의 회의 통화 기능에 관련된 데이터의 입출력 포트, 포트 4는 시험대상인 데이터 출력, 포트 5는 시험결과 데이터 입력, 포트 6은 회의 통화 회로의 정상 동작 상태의 여부 출력 포트이며 포트 7은 중앙 처리 장치(50)의 정상동작 상태 여부의 출력포트이다.The remaining 32 Kbytes of the 8000H-FFFFH are unused and can be used for memory expansion. FIG. 10 is a detailed view of the input / output decoder. FIG. 10a shows a 3-to-8 decoder that actually configures the input / output decoder. As shown in the figure, the decoder receives the output condition of the address buffer 52 and the control buffer 53 as an input and outputs the output.

Is low,

When it is high, the output port is selected by A0-A2. Here, port 0-3 is an input / output port of data related to each conference call function for subhighway 0-3, port 4 is data output to be tested, port 5 is input of test result data, and port 6 is normal of conference call circuit. It is an output port whether it is in an operating state, and port 7 is an output port of whether or not the CPU 50 is in a normal operating state.

11 is a flowchart of the main routine of the functional flow chart of the present invention, in which the data value is written (00) H in the flag area 31 when the power supply of the present invention is turned on or reset. Specific data indicating the normal operation of the central processing unit 50 while waiting for interruption after initializing the RAM area, initializing the test circuit 5 and the conference call circuit 4, indicating that it is ready to receive data. In FIG. 10B, H is outputted through the output point port 7 of the CPU 50 in the normal operation state, and jumps to the interrupt service routine when an interrupt occurs according to data transmission from the upper level.

FIG. 12 shows a flowchart of an interrupt service routine when an interrupt occurs in the main routine flow of FIG. In the figure, reference numeral 80 denotes the first step of the interrupt service routine, 81 denotes the second stage, 82 denotes the third stage, 83 denotes the fourth stage, 84 denotes the fifth stage, and 85 denotes the Steps 6 and 86 represent the seventh step, respectively.

(interrupt right)이 인에이블되어 중앙 처리 장치(50)로 인터럽트를 요구한다. 제(2)단계 (81)은 중앙 처리 장치(50)가 인터럽트를 감지하면, 중앙 처리 장치(50)는 양 방향 RAM(2)의 오른쪽 영역 3FFH(본 장치의 메모리 맵에서는 43FFH)의 데이터를 읽으므로서 인터럽트는 복구되고, 제(3)단계 (82)로 중앙 처리 장치(50)는 플래그 영역인 3FDH(본 장치의 메모리 맵에서는 43FDH)에 (FF)H의 데이터를 쓰므로서 현재 중앙 처리 장치(50)가 인터럽트 서비스 루틴을 수행중임을 상위 레벨이 감지할 수 있도록 하고, 제(4)단계 (83)은 중앙 처리 장치(50)가 데이터를 억세스해야 할 양 방향 RAM(2)의 어드레스를 찾기위한 것으로서, 제(2)단계 (81)에서 읽은 데이터를 왼쪽으로 2번 쉬프트 즉, 데이터에 4를 곱하면 상위 레벨의 A0-A9의 원래 어드레스 값을 찾을 수 있고, 본 장치에서 양 방향 RAM(2)의 오른쪽 메모리 맵은 4000H부터이므로 이 어드레스 값에 4000H를 더하면 억세스하고자 하는 데이터의 어드레스를 구할 수 있다.The first step 80 is to shift the upper level address A0-A9 including the subhighway information and the time slot information in the subhighway two times to the right, that is, dividing A0-A9 by 4 as desired. Eight bits of the valid information A2-A9 become data of the left area 3FFH of the right RAM 2 of the two-way RAM 2, and the upper level writes this information to the 3FFH, so that the right interrupt of the two-way RAM 2 is used. Terminal

(interrupt right) is enabled to request an interrupt to the central processing unit 50. In the second step (81), when the central processing unit 50 detects an interrupt, the central processing unit 50 stores data in the right area 3FFH (43FFH in the memory map of the device) of the two-way RAM 2; The interrupt is recovered by reading, and in the third step (82), the central processing unit 50 writes the data of (FF) H to the 3FDH (43FDH in the memory map of this device) which is a flag area, and is currently centralized. Allow the upper level to detect that the device 50 is executing an interrupt service routine, and step (4) (83) is the address of the two-way RAM 2 where the central processing unit 50 should access the data. By shifting the data read in step (2) to the left twice, i.e., multiplying the data by 4, the original address value of A0-A9 at the upper level can be found, Since the right memory map of RAM (2) is from 4000H, adding 4000H to this address The address of the data to be accessed can be obtained.

(interrupt left)이 인에이블 되고 이 인터럽트에 따라 상위 레벨이 양 방향 RAM(2)의 왼쪽 영역 3FEH의 값을 읽어서 약속된 데이터 값과 비교하여 정상 동작 여부를 확인한다. 이때 상위 레벨이 양 방향 RAM(2)의 왼쪽 영역 3FEH를 읽으므로서 인터럽트는 복귀된다.Step (84) is a step of defining a subroutine for each function according to the function to be performed by the apparatus, and the control message shown in FIG. It reads and jumps to each predetermined subroutine according to this control message. In step (6), in step 85, the subroutine for each function defined in FIG. 5 is performed. In the three-party and conference call connection function, the group designation information of the three-party or conference call transmitted from a higher level, After conducting a three-way or conference call according to attenuation level information, etc., the execution status is checked and the normality of the execution result is output through the output port 6 of the conference call circuit of FIG. 10. This function is used to release time slots for subscribers added to a call or conference call, which are recovered from the conference call.The state function test verifies whether the conference call function is normally performed for a specific time slot as needed. As a function of checking, if a higher level wishes to test this function, the central processing unit 50 may test for a specific time slot. When the test result data is written to the right area 3FEH (43FEH in the memory map of the device) of the bidirectional RAM 2, the left interrupt terminal of the bidirectional RAM 2

(interrupt left) is enabled and according to this interrupt, the upper level reads the value of the left area 3FEH of the two-way RAM 2 and compares it with the promised data value to check whether it is in normal operation. At this time, the interrupt is returned as the upper level reads the left area 3FEH of the two-way RAM 2.

In addition, the self-loopback test function, the loopback test function through the switch network, and the test function of the conference call circuit unit 4 through the switch network as a function of confirming whether the external connection state of the device of the present invention operates normally, the upper level is predetermined If the data is requested and the loopback test is requested, the central processing unit 50 outputs the data through port 4, which is the data output port of the test object of FIG. 10, performs the corresponding test function, and then returns the loopback result to the test result data of FIG. It inputs through port 5, which is an input port, and informs the upper level. The upper level determines the test result by comparing the transmitted data with the received data which is the loopback result data. At this time, the method of notifying the test result to the upper level by the central processing unit 50 is the same as in the above state function test. Thus, after performing each function of the (6) step 85, as the (7) step 86, the central processing unit writes data of (00) H to the flag area 31 so that the interrupt service routine at a higher level is performed. It informs the end so that a new interrupt can be generated and then returns from the interrupt service routine.

및 어드레스 신호 A4의 제어에 의해서 N-1 가산 방식으로 회의 통화 기능을 수행한 후, 회의통화 결과 음성 신호는 본 발명에 사용한 회의통화 소자의 특성으로 인하여 입력 타임슬롯에 대하여 1 타임슬롯 지연된 신호로서 회의통화 동기 신호 발생기(93)에서 공급된 회의 통화용 동기신호와 회의통화용 시스템 클럭에 동기를 맞추어 64Kbps의 전송속도로 차분신호 구동기(91)를 통하여 차분레벨 신호로서 스위치 네트워크로 출력된다.FIG. 13 is a block diagram of a conference call circuit section, in which 90 is a conference call unit consisting of four conference call elements, 91 is a differential signal driver, 92 is a differential signal receiver, and 93 is a conference call. Each sync signal generator is shown. The conference call survey constituting the conference call unit 90 performs a conference call function for one PCM subhighway, 32 time slots. The entire operation is performed by converting the PCM voice signal inputted from the switch network in the form of a differential signal to the TTL level of the differential signal receiver 92, and then inputting it to each conference element, which is inputted to the conference call function of FIG. After the conference call element is selected by the related input / output port, port 0-3, the two-way data D0-D7 of the CPU 50, the control signal

And after performing the conference call function by the N-1 addition method under the control of the address signal A4, the conference call result voice signal is a signal delayed by one time slot with respect to the input timeslot due to the characteristics of the conference element used in the present invention. In synchronism with the conference call synchronization signal supplied from the conference call synchronization signal generator 93 and the conference call system clock, the difference signal is outputted to the switch network through the differential signal driver 91 at a transmission rate of 64 Kbps.

14 is a block diagram of a test circuit unit, which is largely a test data transmitter, a test data output unit, a test data receiver, a test interval generator and sub highway decoder, a conference pass output control unit, a loopback data output unit through a switch network, and loopback data through a switch network. It consists of an input section and a test result input section of the conference call circuit section through the switch network.

In the drawing, reference numeral 100 denotes a test data transmission unit, 100a denotes a test data latch buffer, 100b denotes a parallel / serial conversion circuit, 100c denotes a parallel / serial conversion control circuit, and 101 denotes a test data output unit. Reference numeral 101a denotes a test data output buffer, 101b denotes a test data output buffer control circuit, 102 denotes a test data receiver, 102a denotes a serial / parallel conversion circuit, 102b denotes a test result data buffer, and 102c. Is a test result data latch buffer control circuit, 103 is a test interval generation and subhighway decoder, 103a is a time slot 0 interval generation circuit 103b is a 1 timeslot delay circuit, 103a is a subhighway decoder 0, Numeral 103d denotes a subhighway decoder 1, 104 a conference call output controller, 104a an output buffer 0, 104b an output buffer 0 control circuit, 105 a loopback data output through a switch network, 105a is output buffer 1, 105b is output buffer 1 control circuit 106 is loopback through the switch network The data input unit 106a is input buffer 0, 106b is input buffer 0 control circuit 107 is the test result of the conference call circuit unit through the switch network, the input unit 107a is the input buffer, and 107b is input buffer 1 control. Each circuit is shown.

The test data transmitter 100 is configured to latch test data input in parallel through the data buses D0-D7 of the central processing unit 50 by selection of port 4, which is a test data output port of FIG. 100a), a parallel / serial conversion unit 100b for converting parallel test data into serial test data for looping back, and a parallel / serial conversion control circuit 100c for controlling the output of the parallel / serial conversion unit. Control of the signal generated by the time slot 0 section generating circuit 103a and the latched data signal D0 of the serial data converted by the channel frame synchronization signal (8KHz) and the system clock (2.048MHz) supplied from the switch network of the switch. The test data output unit 101 outputs to the test data output unit 101.

The test data output unit 101 receives a test test data output buffer 101a which is a three state buffer and a signal in which the latched data signals D4 and D6 are inverted to determine an output direction of the test data to the OR gate. The test data output buffer control circuit 101b controls the test data output buffer 101a as its output.

The test data receiving unit 102 converts various loopback result data input in serial form into parallel data by the serial / parallel conversion circuit 102a, and then the serial data is latched by the test result data latch buffer control circuit 102c. According to the function, the test result is latched to the test data latch buffer 102b and read into the CPU 50 by the selection of port 5, which is the test result data input port of FIG.

The test interval generation subhighway decoder is composed of a time slot 0 section generation circuit 103a, a western highway decoder 0 103c, a one time slot delay circuit 103b, and a subhighway decoder 1 103d. As a functional unit that performs a function of selecting a time slot in the subhighway, the apparatus of the present invention used time slot 0 of each subhighway as a test object. The timeslot 0 section generating circuit 103a and the subhighway decoder 0 103c generate a timeslot 0 section to be tested by the system clock and the channel frame synchronizing signal, and use it as an enable signal of the subhighway decoder 0 103c. Selects the subhighway, and the 1 timeslot delay circuit 103b and the subhighway decoder 1 103d are arranged in a conference call circuit according to a 1 timeslot delay between the input time slot and the output timeslot of the conference call circuit 4. In order to test the loopback test result for 4), the signal generated by the time slot 0 section generating circuit 103a is delayed by 1 time slot (8 system clock) and used as an enable signal of the subhighway decoder 1 103d. Select the subhighway.

Next, a description of the data signals D0-D7 latched in the test result data latch buffer used as enable signals of various control circuits and the circuit test contents thereby will be described in detail.

D0-D7, which is used as an enable signal of various control circuits, is a data signal latched in the test data latch buffer. D0 controls the output terminal of the parallel / serial conversion circuit 100b so that when D0 is low, it is enabled and high. It is disabled in the state, and D1 and D2 are used for subhighway selection, and D3 controls the time slot 0 section generating circuit 103a and the master reset terminal to turn it low. This function is used to generate another slot 0 section by driving when it is high. In addition, D4-D6 controls various loopback paths, and output buffer 0 104a, output buffer 105a 1, input buffer 0 106a, and input buffer 1 107a are three-state buffers in the state of D4-D6. When each of the control buffers determined according to the state is low, each buffer is enabled. When the control state is high, the control buffers are disabled so that the output of each buffer becomes high impedance. The case of the case is explained.

First, when the test is not performed, output buffer 0 (104a) of the conference call output controller 104 is enabled so that the conference call output should be transmitted to the switch network through the differential signal driver 91, wherein the central processing unit ( 50) controls D7-D0 to have 11110001B (F1H) so that time slot 0 section generation circuit 103a is reset when D3 is low so that the outputs of subhighway decoder 0 103c are all high. An output signal inverting the output to a low state through an inverter and four low states driving D4 as an input of an AND gate enable the output buffer 0 to transmit the conference call output to the switch network.

Second, the self loopback test is a function for self-diagnosis of various functional parts of the apparatus of the present invention. The test data output buffer 101a is enabled so that the test data does not go through an external loopback path. In this case, the upper level is the output of the test data output buffer control circuit 101b composed of an OR gate whose inputs are the inverted signals of the controllers D4 and D6 so that the D7-D0 has 11101000B (E8H). Since the test data output buffer 101a is enabled and D4 is low, the output buffer 0 104a is enabled so that the conference call output is output to the switch network, and the output buffer 1 control circuit 105b is set to D5 and D6. The input AND gate output and the output of subhighway decoder 0 (103c) become OR gate inputs, and in the case of self loopback test, the output of the output buffer 1 control circuit 105b becomes high. And disabling the output buffer 1 (105a).

Third, the loopback test through the switch network outputs test data transmitted by a higher level to the switch network through the loopback data output unit 105 through the switch network, thereby providing a differential signal receiver 92 and a loopback data input unit through the switch network ( After latching the test data input through the test data receiving unit 106 in the central processing unit 50 to read the test result data to the upper level, the upper level is D11-D0 11011XX0B (D2 and D1 of XX) If the value is 00, the subhighway 0 is selected, the subhighway 1 is selected from 01, the subhighway 2 is selected from 10, and the subhighway 3 is selected from 11) .The time slot 0 of the subhighway under test is selected by the D2 and D1 values. . In addition, since the output of the test data output buffer control circuit 101b becomes high because D4 and D6 are high, the test data output buffer 101a is disabled, and the output buffer 0 104a is selected as the subhighway timeslot 0. Disabled during the interval, Output Buffer 1 105a is enabled for the selected subhighway timeslot 0 interval, so that test data is output to the switch network, and the test data is looped back in the switch network and loopback data input through the switch network ( 106).

Here, the output of the subhighway 0 decoder 103c and the output of the input buffer 0 control circuit 106b composed of an OR gate of which the inverted signals of D5 and D6 are input enable the input buffer 0 106a so that the test target sub The data of timeslot 0 in the highway is outputted to the test data receiving unit 102.

Fourth, the test of the conference call circuit unit through the switch network outputs the test data transmitted by the upper level to the switch network through the loopback data output unit 105 through the switch network, thereby conferencing the difference signal receiver 92 with the switch network. The test data input through the test result input unit 107 of the communication circuit unit latches the test data in the test data receiving unit 102, and then the central processing unit 50 reads the test result data and notifies the upper level as a higher level. D0 is controlled to have 10011XX0B (subhighway 0 when XX D2 and D1 value is 00, subhighway 1 when 01, subhighway 2 when 11, and subhighway 3 when 11, respectively). Subhighway timeslot 0 is selected. In addition, since the output state of the test data output buffer control circuit 101b becomes high because D4 is high and D6 is low, the test data output buffer 101a is disabled and the output buffer 0 104a is selected as the subhighway time. Disabled during slot 0 interval, output buffer 1 105a is enabled for the selected subhighway timeslot 0 interval, so that test data is output to the switch network, and this data is looped back in the switch network to provide conference call circuitry over the switch network. The test result is input to the input unit 107. Here, the output of the sub-highway decoder 1 (103d) and the output of the input buffer 1 control circuit (107b) consisting of an OR gate of which D5 and D6 are inputs enable the input buffer 1 (107a) for the selected subhighway to be tested. After the data of timeslot 0 in the subhighway performs the conference call function, the data of timeslot 1 whose data is delayed by 1 timeslot is output to the test data receiving unit 102.

In the third and fourth cases above, the data whose test results are latched in the data latch buffer 102b is outputted by the time slot 0 section generation circuit 103a output signal and one time slot delay circuit 103b output signal controlled by D6. If D6 is high, latch the timeslot 0 data, which is the loopback test data through the switch network, and if D6 is low, latch the data of timeslot 1, the test result data of the conference call circuit through the switch network, and central processing. It is read by the device 50. The central processing unit 50 which has performed such various test functions transmits the 11110001B (F1H) value to the test data transmitter to disable the output of the parallel / serial conversion circuit 100b according to the high state of D0, and D3 is low. Disabling the subhighway decoders 103c and 103d according to the master reset of the timeslot zero section generating circuit 103a according to the state, and the output of the subhighway decoders 103c and 103d accordingly becomes a high state so that the conference call circuit unit Output buffer 0 (a) of (4) is all enabled to enable normal conference call function.

The alarm circuit unit generates alarm for system clock, channel frame synchronization signal is not supplied, alarm for abnormal state of upper level transmission clock, alarm for abnormal operation of central processing unit, and alarm for malfunction of conference call circuit. When an alarm is generated for each of these functions, the alarm collection device of the exchange system sends information on the alarm of the device and turns on the light emitting diode to designate the function that has occurred and notify the operator.

As described above, the apparatus of the present invention adopts the N-1 addition method, which has excellent naturalness, to enhance the quality of service of the conference call, and to adjust the attenuation of the voice signal level, which is a problem of this method, according to the number of participants. The shortcomings of the method were solved. In addition, as the conference call is carried out in the variable timeslot, the efficiency of the timeslot is increased, and the configuration of the device is digitalized to increase the density of the circuit pack, thereby adding economical efficiency, and strengthening various functional circuits and alarm circuits, making maintenance easy. And to operate as a reliable device.

Claims (27)

A high level matching means 1 for converting various types of commands of a high level into a suitable form, and a bidirectional RAM connected to the high level matching means 1 for storing various types of information and high level information for mutual communication; 2) connected to the two-way RAM (2), and connected to the central control means (3), the central control means (3) for interpreting commands stored in the two-way RAM (2) to control the associated circuits. Conferencing call means 4 for performing a conference call function under the control of the central control means 3, and connected to the central control means 3 to perform a test function under the control of the central control means 3; A digital conference call device for an electronic switching system, characterized in that it comprises test and alarm means (5) for performing and collecting alarms of critical parts. The differential level transceiver (1) according to claim 1, wherein the higher level matching means (1) is connected to a differential signal transceiver (10) and a differential signal transceiver (10) for performing mutual conversion between a higher level difference level signal and a TTL level signal. A serial / parallel converting means 11 of address / mode for converting address and mode signals received in serial form from a level into a parallel form, and a circuit of several circuit packs connected to the serial / parallel converting means 11; A circuit pack selecting means 12 for determining whether the pack is to perform a conference call function, and connected to the circuit pack selecting means 12 for generating a signal informing that the pack is ready to transmit or receive data at a higher level Transmitting and ready state generator 13, which is connected to the differential signal transceiver 10 for converting the serial data received from the upper level in parallel form to latch Serial / parallel converting means 14 of the received data for performing a function, the differential signal transceiver 10 and serial / parallel converting means 14 connected to convert data in parallel form to be transmitted at a higher level into serial form. Connected to the parallel / serial conversion circuit 11 of the transmission data, the serial / parallel conversion means 14 of the received data, and the parallel / serial conversion circuit 15 of the transmission data to select a function to be performed by a higher level. And an interrupt circuit (18) connected to the mode selection decoder (16) and the differential signal transceiver (10) for informing a high level of interrupt signals generated for various test results. Digital conference call device. According to claim 1, wherein said central control means (3) comprises a central processing unit (50), a data buffer (51) and an address buffer (52) and a control buffer (53) connected to said central processing unit (50), and said address. A memory control circuit 54 connected to a buffer 52 and a control buffer 53, an input / output decoder 55 connected to the control buffer 53, the data buffer 51, a memory control circuit 54, and an input / output decoder ( A ROM 56 connected to 55, a RAM 57 connected to the ROM 56, a data buffer 51, a memory control circuit 54, a central processing unit 50, and a control buffer 53, and the central processing. And a clock generator circuit (58) for the central processing unit connected to the device (50), and an initialization and reset circuit (59) connected to the central processing unit (50). 2. The circuit communication device according to claim 1, wherein the circuit communication means (4) comprises at least one conference element (90), a differential signal receiver (92) connected to the conference element (90), and a difference connected to the conference element (90). A digital conference telephone apparatus for an electronic exchange comprising a signal driver (91) and a conference call synchronization circuit generator (93) connected to the circuit communication element (90). According to claim 1, wherein the test and alarm means (5) is composed of a test circuit and an alarm circuit, the test circuit is a test data transmission means 100, the test data output means 101 connected to the transmission means 100 ), Test data receiving means (102) connected to the output means (101), test interval generation and subhighway decoder (103) connected to the transmitting means (100), test interval generation and subhighway with the transmitting means (100). Conference call output control means (104) connected to the decoder (103), loopback data output means (105) via a switch network connected to the transmitting means (100) and the subhighway decoder (103) and output control means (104), Loopback data input means 106 via a switch network connected to test data output means 101, test data receiving means 102 and subhighway decoder 103, and the transmission reception 100 and subhighway decoder 103 And Peubaek electronic exchange appointed digital conference call device, characterized in that consists of a data input unit 106, the test result meeting the input unit 107 of the call means 4 through the switch network connected to. The address according to claim 1 or 2, wherein the address between the upper level matching means (1) and the two-way RAM (2) includes circuit pack selection information, in-package subhighway selection information, and timeslot information. Digital conference telephone apparatus for an electronic exchange, characterized in that for determining the position to write the data using the upper level. 7. The electronic exchange according to claim 6, characterized in that the left area of the two-way RAM 2 is divided into a data reception area, a flag area, and an interrupt area related to a conference call according to the address appointment form. Digital conference call device. 8. The method of claim 7, wherein the data reception area related to the conference call is divided into four subhighways for each subhighway, and the area in each subhighway is divided into respective time slots, and 4 bytes are provided for each time slot in each subhighway. A digital conference call device for an electronic exchange, characterized in that the assignment. 8. The method according to claim 7, wherein the 3FD address of the two-way RAM 2 is designated as a flag area, and if the data of this area is (00H), the upper level can transmit data, and if FF (H), data can be transmitted. A digital conference call device for an electronic exchange, characterized in that the use of a flag to confirm receipt of data. The method according to claim 7, wherein a total of 10 bits of addresses A0 to A9 of the address are shifted to the right twice to be 8 bits, and then an interrupt occurs by writing the 8 bits as data of address 3FF which is an interrupt area. A digital conference call device for an electronic exchange, characterized in that the processing device notifies that data has been received from a higher level. 4. The digital conference call device according to claim 3, wherein the INTR terminal, which is the interrupt generating terminal of the RAM which is the right area of the bidirectional RAM 2, is directly connected to the interrupt terminal of the central processing unit 50. . 4. The data buffer 51 according to claim 3, wherein the data buffer 51 is configured to be connected to an AND gate and an OR gate which input at least one control signal so that the data buffer is in a reception state or a transmission state according to the output of the AND gate. Digital conference telephone apparatus for an electronic exchange, characterized in that the configuration. 4. The memory control circuit according to claim 3, wherein the memory control circuit (54) comprises a higher address signal (A14, A15) and a control circuit (

Digital conference telephone apparatus for an electronic exchange, characterized in that to distinguish the address of the ROM (56) and RAM (57). The input / output decoder 55 further comprises four address signals and a control signal.

Each input / output port is determined by a), the selection of the conference call means 4, the output selection of the data to be tested, the test result data input selection, the normal operation state output selection of the conference call means 4, the central processing unit A digital conference telephone apparatus for an electronic exchange, characterized in that the output of the normal operation state of 50 is selected. 4. The main routine of the central processing unit (50) according to claim 3, wherein the main routine of the central processing unit (50) comprises: a flag value, initialization of the RAM (57), test and alarm means (5) and conference call means (4), and the central processing unit (50). A digital conference call device for an electronic exchange, characterized in that it has an output of whether or not normal operation is performed and an interrupt routine has a function of jumping. The interrupt service routine of the CPU comprises: a routine for reading the RAM (57) data, a routine for setting a flag, a routine for shifting the read data two bits to the left, and each sub according to a control message. A digital conference telephone apparatus for an electronic exchange comprising a routine and a routine for resetting a flag. 17. The method of claim 16, wherein the routine for reading data from the RAM 57 detects an interrupt signal requested by the CPU 50 at a higher level to read the data in the interrupt area so that the interrupt is recovered. Digital conference call device for electronic exchange. 17. The system of claim 16, wherein the flag setting routine writes (FF) H to a flag area of the bidirectional RAM 2 to inform the central processor that it is currently executing an interrupt service routine. A digital conference call device for an electronic switch, characterized in that it has a function to prohibit a new interrupt generation. The routine of claim 16, wherein the routine for shifting the read data two bits to the left obtains an original address value designated by a higher level, which is a result of shifting the data read from the RAM 57 to the left two bits, and then returns to this value. And an address area of the RAM (57) to be accessed by the CPU (50) by adding the initial address value 4000H assigned to the RAM (57). 17. The method of claim 16, wherein each service routine according to the control message includes a three-way call connection, a conference call connection, a release, a state test function, a self loopback test function, a loopback test function through a switch network, and a conference call through a switch network. A test conference of the means (4), characterized in that for performing a subroutine for each function in accordance with a control message. 17. The digital switch of claim 16, wherein the flag resetting routine has a function of resetting a flag area to (H) after performing an interrupt service so that a higher level can generate a new interrupt. Conference device. 6. The digital conference call according to claim 5, wherein the initialization of the test circuit initializes the function of the test circuit by transmitting data F1H transmitted from the central control means (3) to the test circuit. Device. 21. The self loopback test according to claim 20, wherein in the self-loopback test, the upper level transmits E8H as test data to the test and alarm means 5, and the test path is determined by the test data, and the central processing unit 50 loops back. A digital conference call device for an electronic exchange comprising reading the result data and notifying it to a higher level. 21. The loopback test via the switch network according to claim 20, wherein the upper level transmits 11011XX0B as test data to the test and alarm means 50, and the test path is determined by the test data. C) reads the loopback result data through the switch network and notifies to a higher level. 21. The test of the conference call circuit via the switch network according to claim 20, wherein the upper level transmits 10011XX0B as test data to the test and alarm means 5, and the test path is determined by the test data. A digital conference call device for an electronic exchange, characterized in that the device (50) reads the test result data of the conference call means (4) through the switch network and notifies it to a higher level. 3. A digital conference call device according to claim 2, wherein the differential signal transceiver (10) comprises two differential signal receivers and two differential signal transmitters. 27. The N-1 addition method according to claim 26, wherein the voice signal input through the differential signal receiver performs a conference call function for one subhighway per conference pass element by the control of the central control means 3, respectively. The digital conference call device for an electronic exchange, characterized in that for outputting a mixed voice signal in accordance with the conference call synchronization signal through the differential signal driver.

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