KR910019787A - ROM Addressing Conversion Method and Circuit in Printer - Google Patents

ROM Addressing Conversion Method and Circuit in Printer Download PDF

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Publication number
KR910019787A
KR910019787A KR1019900007536A KR900007536A KR910019787A KR 910019787 A KR910019787 A KR 910019787A KR 1019900007536 A KR1019900007536 A KR 1019900007536A KR 900007536 A KR900007536 A KR 900007536A KR 910019787 A KR910019787 A KR 910019787A
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South Korea
Prior art keywords
rom
version
cpu
gate
address
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KR1019900007536A
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Korean (ko)
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KR930003440B1 (en
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김광석
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정용문
삼성전자 주식회사
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Priority to KR1019900007536A priority Critical patent/KR930003440B1/en
Publication of KR910019787A publication Critical patent/KR910019787A/en
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Publication of KR930003440B1 publication Critical patent/KR930003440B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)

Abstract

내용 없음No content

Description

프린터에 있어서 롬 어드레싱 변환방법 및 회로ROM Addressing Conversion Method and Circuit in Printer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 회로도, 제2도는 본 발명에 따른 회로도, 제3도는 본 발명에 따른 중앙처리장치(CPU)에 의한 할당되는 맵도.1 is a conventional circuit diagram, FIG. 2 is a circuit diagram according to the present invention, and FIG. 3 is a map diagram assigned by a central processing unit (CPU) according to the present invention.

Claims (3)

프린터의 중앙처리장치(CPU)에 의한 롬(ROM)어드레싱 회로에 있어서, 상기 중앙처리(CPU)가 상기 롬(ROM)의 공통부분을 어드레싱하는 공통수단과, 상기 중앙처리장치(CPU)의 버젼 선택 어드레스신호와 사용자의 버젼 선택에 의해 상기 롬(ROM)의 각 다른 버젼을 선택하는 버젼 선택수단으로 구성됨을 특징으로 하는 프린터에 있어서 롬 어드레싱 변환회로.In a ROM addressing circuit by a central processing unit (CPU) of a printer, common means for the CPU to address a common part of the ROM, and a version of the central processing unit (CPU). And a version selecting means for selecting different versions of the ROM by means of a selection address signal and a user's version selection. 제1항에 있어서, 버젼 선택수단이 중앙처리장치(CPU)의 어드레스버스(A0-A13)를 롬(ROM)의 어드레스버스(A0-A13)에 일치되도록 연결하고, 중앙처리장치(CPU)의 어드레스버스(A15)를 앤드게이트(AN1)와 롬(ROM)의 어드레스버스(A14)에 연결하며, 상기중앙처리장치(CPU)의 어드레스버스(A14)를 상기 앤드게이트(AN1)의 입력단에 연결하고, 상기 앤드게이트(AN1)의 출력을 오아게이트(OR1)의 입력단에 연결하고, 딮 스위치(D/S)의 선택 출력단에 풀업저항(R1)을 접속후 상기 오아게이트(OR1)의 입력단에 연결하며, 상기 오아게이트(OR1)의출력단을 롬(ROM)의 어드레스 버스(A15)에 접속시켜 구성됨을 특징으로 하는 회로.The CPU of claim 1, wherein the version selecting means connects the address buses A0-A13 of the central processing unit (CPU) to match the address buses (A0-A13) of the ROM (ROM). The address bus A15 is connected to the AND gate AN1 and the address bus A14 of the ROM, and the address bus A14 of the central processing unit CPU is connected to the input terminal of the AND gate AN1. The output of the AND gate AN1 is connected to the input terminal of the OR gate OR1, the pull-up resistor R1 is connected to the select output terminal of the switch D / S, and then connected to the input terminal of the OR gate OR1. And the output terminal of the OR gate (OR1) is connected to an address bus (A15) of a ROM. 롬 어드레싱 방법에 있어서, 상기 롬의 공통되는 버젼을 따로 분리하는 과정과, 상기 분리된 공통 영역을 항상 선택 어드레싱 하는 과정과, 상기 공통 이외의 버젼 선택 신호를 입력하는 과정과, 상기 버젼 선택신호와 상기 발생되는 어드레싱신호를 논리화하여 상기 롬의 각 버젼에 따라 다른 부분의 버젼을 선택하는 과정으로 이루어짐을 특징으로 하는 프린터에 있어서 롬 어드레싱 변환방법.A ROM addressing method comprising the steps of: separating a common version of the ROM separately; always selecting addressing the separated common region; inputting a version selection signal other than the common; And a version of a different part is selected according to each version of the ROM by logicalizing the generated addressing signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900007536A 1990-05-24 1990-05-24 Rom adressing transform method and its circuit KR930003440B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900007536A KR930003440B1 (en) 1990-05-24 1990-05-24 Rom adressing transform method and its circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900007536A KR930003440B1 (en) 1990-05-24 1990-05-24 Rom adressing transform method and its circuit

Publications (2)

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KR910019787A true KR910019787A (en) 1991-12-19
KR930003440B1 KR930003440B1 (en) 1993-04-29

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Application Number Title Priority Date Filing Date
KR1019900007536A KR930003440B1 (en) 1990-05-24 1990-05-24 Rom adressing transform method and its circuit

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KR930003440B1 (en) 1993-04-29

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