KR910019203A - Input protection circuit manufacturing method - Google Patents
Input protection circuit manufacturing method Download PDFInfo
- Publication number
- KR910019203A KR910019203A KR1019900005060A KR900005060A KR910019203A KR 910019203 A KR910019203 A KR 910019203A KR 1019900005060 A KR1019900005060 A KR 1019900005060A KR 900005060 A KR900005060 A KR 900005060A KR 910019203 A KR910019203 A KR 910019203A
- Authority
- KR
- South Korea
- Prior art keywords
- protection circuit
- circuit manufacturing
- input protection
- diode
- well
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000009792 diffusion process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제 3 도는 본 발명의 설계도, 제 4 도는 제 3 도의 회로도.3 is a schematic diagram of the present invention, and FIG. 4 is a circuit diagram of FIG.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900005060A KR0166805B1 (en) | 1990-04-12 | 1990-04-12 | Method for manufacturing input protection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900005060A KR0166805B1 (en) | 1990-04-12 | 1990-04-12 | Method for manufacturing input protection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910019203A true KR910019203A (en) | 1991-11-30 |
KR0166805B1 KR0166805B1 (en) | 1999-01-15 |
Family
ID=19297937
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900005060A KR0166805B1 (en) | 1990-04-12 | 1990-04-12 | Method for manufacturing input protection circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0166805B1 (en) |
-
1990
- 1990-04-12 KR KR1019900005060A patent/KR0166805B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0166805B1 (en) | 1999-01-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20050824 Year of fee payment: 8 |
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LAPS | Lapse due to unpaid annual fee |