KR910013888A - Synchronous Receive Circuit Using Upconversion - Google Patents

Synchronous Receive Circuit Using Upconversion Download PDF

Info

Publication number
KR910013888A
KR910013888A KR1019890020143A KR890020143A KR910013888A KR 910013888 A KR910013888 A KR 910013888A KR 1019890020143 A KR1019890020143 A KR 1019890020143A KR 890020143 A KR890020143 A KR 890020143A KR 910013888 A KR910013888 A KR 910013888A
Authority
KR
South Korea
Prior art keywords
circuit
signal
pass filter
voltage controlled
low pass
Prior art date
Application number
KR1019890020143A
Other languages
Korean (ko)
Inventor
김차배
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019890020143A priority Critical patent/KR910013888A/en
Priority to JP2406124A priority patent/JPH04227339A/en
Publication of KR910013888A publication Critical patent/KR910013888A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

내용 없음.No content.

Description

업컨버젼을 이용한 동기 수신회로Synchronous Receive Circuit Using Upconversion

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 회로도.2 is a circuit diagram according to the present invention.

Claims (3)

안테나(ANT2)와, 제1로우패스필터(10)와, 고주파 중폭부(20)와 제1믹서(30)와, 단간동조부 (40)와 국부발진 주파수(50)와, PLL회로(60)로 구성된 업턴버젼회로(A)를 구비한 동기 수신회로에 있어서, 상기 업컨버젼회로(A)의 출력인 중간주파수를 입력하여 베이스밴드신호로 변환하여 출력하는 베이스밴드 변환부(Bl)와, 상기 업컨버전회로(A)의 출력인 중간주파수와 상기 베이스밴드 변환부(B1)의 전압제어 발진신호를 입력하여 위상에러를 검출하여 상기 베이스밴드 변환부(B1)로 피드백시키는 위상에러 검출부(B2)로 구성됨을 특징으로 하는 회로.An antenna ANT2, a first low pass filter 10, a high frequency medium width section 20, a first mixer 30, an inter-step tuning section 40, a local oscillation frequency 50, and a PLL circuit 60 A synchronous receiving circuit having an upturn version circuit (A) comprising: a baseband converter (Bl) for inputting an intermediate frequency which is an output of the upconversion circuit (A), converting it into a baseband signal, and outputting the baseband signal; A phase error detection unit B2 for inputting an intermediate frequency, which is the output of the upconversion circuit A, and a voltage controlled oscillation signal of the baseband conversion unit B1 to detect a phase error and feeding it back to the baseband conversion unit B1. A circuit comprising: 제1항에 있어서, 베이스밴드 변환부(B1)가 전압제어 발진신호를 발생하는 전압제어 발진기(100)와, 상기 전압제어 발진기(100)의 발진신호와 상기 업컨버젼회로(A)에서 출력된 동조신호를 입력하여 믹싱하여 출력하는 제2믹서(70)와, 상기 제2믹서(70)에서 믹싱된 신호를 필터링 하는 제2로우패스필터(80)와, 상기 로우패스필터(80)에서 필터링된 신호를 증폭출력하는 밴드패스 증폭기(90)로 구성됨을 특징으로 하는 회로.The oscillator of claim 1, wherein the baseband converter B1 outputs a voltage controlled oscillator 100 for generating a voltage controlled oscillation signal, an oscillation signal of the voltage controlled oscillator 100, and the upconversion circuit A. A second mixer 70 for inputting and mixing tuning signals, a second low pass filter 80 for filtering signals mixed in the second mixer 70, and filtering in the low pass filter 80 And a band pass amplifier (90) for amplifying and outputting the signal. 제1항에 있어서, 위상에러 검출부(B2)가 90°위상 지연된 신호를 출력하는 위상이동기(110)와, 상기 위상이동기(110)에서 90°위상이 지연된 신호와 상기 업컨버젼회로(A)의 출력신호를 믹싱하여 출력하는 제3믹서(120)와, 상기 제3믹서(120)에서 믹싱된 신호를 필터링하여 전압제어 발진기(100)로 피드백 시키는 제3로우패스필터(130)로 구성됨을 특징으로 하는 회로.The phase shifter 110 of claim 1, wherein the phase error detector B2 outputs a signal delayed by 90 degrees, the signal delayed by 90 degrees in the phase shifter 110, and the upconversion circuit A. And a third low pass filter 130 for mixing and outputting an output signal and a third low pass filter 130 for filtering the mixed signal from the third mixer 120 and feeding it back to the voltage controlled oscillator 100. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020143A 1989-12-29 1989-12-29 Synchronous Receive Circuit Using Upconversion KR910013888A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019890020143A KR910013888A (en) 1989-12-29 1989-12-29 Synchronous Receive Circuit Using Upconversion
JP2406124A JPH04227339A (en) 1989-12-29 1990-12-25 Synchronous reception circuit utilizing up- conversion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020143A KR910013888A (en) 1989-12-29 1989-12-29 Synchronous Receive Circuit Using Upconversion

Publications (1)

Publication Number Publication Date
KR910013888A true KR910013888A (en) 1991-08-08

Family

ID=19294170

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020143A KR910013888A (en) 1989-12-29 1989-12-29 Synchronous Receive Circuit Using Upconversion

Country Status (2)

Country Link
JP (1) JPH04227339A (en)
KR (1) KR910013888A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272977A (en) * 1992-02-05 1993-12-28 Toshiba Kikai Kabushiki Kaisha Printing plate mounting apparatus, printing plate replacement apparatus and printing plate replacement method
JPH1117749A (en) * 1997-06-24 1999-01-22 Nec Corp Demodulation circuit

Also Published As

Publication number Publication date
JPH04227339A (en) 1992-08-17

Similar Documents

Publication Publication Date Title
KR100533626B1 (en) Quadrature signal generator with feedback type frequency doubler
MY123208A (en) Direct conversion receiver
SE9102317D0 (en) MIXERS FOR DIRECT CONVERSION RECEIVERS
KR960016174A (en) Correction circuit for mixer circuit, double super heterodyne receiver using correction circuit, frequency spectrum conversion circuit using correction circuit
CA2065758A1 (en) Dual port oscillator for two-stage direct conversion receiver
KR890006069A (en) Double branch receiver
KR910016195A (en) TV reception saxon
TW341011B (en) AM radio receiver
AUPM587094A0 (en) Microwave loop oscillators
KR900008789A (en) Direct Mixed Synchronous AM Receiver
WO2001058103A3 (en) Kaskadenfrequenzumsetzer unter verwendung von phasenverschobenen signalen der lokalen oszillatoren
KR910013888A (en) Synchronous Receive Circuit Using Upconversion
CA2161846A1 (en) Television receiver
KR960020416A (en) Signal detector
KR950003840A (en) Broadband radar detector
KR960039654A (en) Phase Locked Loop of Microwave Oscillators
JP2003124834A (en) Ic input circuit for tuner
KR960036346A (en) Satellite broadcasting receiver
KR960027408A (en) Satellite frequency converter
KR970055244A (en) Improved Frequency Inverter of Satellite Receiver
KR0143727B1 (en) Frequency Oscillator of Satellite Communication System
KR910011032A (en) TV high frequency signal processing system using single conversion method
KR910013700A (en) Direct synchronous receiving circuit
KR950010392A (en) Frequency tuning device of double conversion tuner
KR970055687A (en) Intermediate Frequency Generation Circuit of Wireless Communication System

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19891229

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid