KR910013741A - Step Tone Oscillator Circuit - Google Patents

Step Tone Oscillator Circuit Download PDF

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Publication number
KR910013741A
KR910013741A KR1019890018084A KR890018084A KR910013741A KR 910013741 A KR910013741 A KR 910013741A KR 1019890018084 A KR1019890018084 A KR 1019890018084A KR 890018084 A KR890018084 A KR 890018084A KR 910013741 A KR910013741 A KR 910013741A
Authority
KR
South Korea
Prior art keywords
divided
output
oscillator circuit
reference frequency
tone oscillator
Prior art date
Application number
KR1019890018084A
Other languages
Korean (ko)
Inventor
권영호
이근양
Original Assignee
홍종선
금성전선 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 홍종선, 금성전선 주식회사 filed Critical 홍종선
Priority to KR1019890018084A priority Critical patent/KR910013741A/en
Publication of KR910013741A publication Critical patent/KR910013741A/en

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

내용 없음.No content.

Description

스텝 톤 발진회로Step Tone Oscillator Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 원리도,1 is a principle diagram of the present invention,

제2도는 본 발명의 출력 파형과 PLL 발진 주파수의 관계를 설명하기 위한 파형도.2 is a waveform diagram for explaining the relationship between the output waveform and the PLL oscillation frequency of the present invention.

Claims (3)

발진부(10)의 출력을 제1분주기(20)에서 기준주파수(fref)로 분주하고, PLL회로(30)에서는 분주된 기준주파수(fref)의 N배 출력을 하고, 제2 분주기 및 카운터(40)에서 상기 N배 출력을 n배 분주 및 카운트 한다음, 각 타운트 값에 따라 이피롬(50)에서 디지타이징된 값을 가지며, 이를 D/A 컨버터(60)에서 아날로그 신호로 바꾼 다음 증폭시켜서된 스텝톤 발진회로.The output of the oscillator 10 is divided by the first frequency divider 20 at a reference frequency fref, and the PLL circuit 30 outputs N times the divided reference frequency fref, and the second divider and counter At 40, the N-times output is divided and counted n-fold times, and has a digitized value in the pyrom 50 according to each town value, which is converted into an analog signal in the D / A converter 60 and then amplified Steptone oscillation circuit. 제1항의 기준주파수(fref)의 N배 출력에 있어서, N은 가변될수 있는 임의의 수인것.N output of the reference frequency fref of claim 1, where N is any number that can be varied. 제1항의 n배 분주에 있어서, n은 가변될 수 있는 임의의 수인것.The n-fold division of claim 1, wherein n is any number that can be varied. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890018084A 1989-12-05 1989-12-05 Step Tone Oscillator Circuit KR910013741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890018084A KR910013741A (en) 1989-12-05 1989-12-05 Step Tone Oscillator Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890018084A KR910013741A (en) 1989-12-05 1989-12-05 Step Tone Oscillator Circuit

Publications (1)

Publication Number Publication Date
KR910013741A true KR910013741A (en) 1991-08-08

Family

ID=67662524

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890018084A KR910013741A (en) 1989-12-05 1989-12-05 Step Tone Oscillator Circuit

Country Status (1)

Country Link
KR (1) KR910013741A (en)

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E601 Decision to refuse application