KR910013350U - Real-time domain division circuit - Google Patents
Real-time domain division circuitInfo
- Publication number
- KR910013350U KR910013350U KR2019890019463U KR890019463U KR910013350U KR 910013350 U KR910013350 U KR 910013350U KR 2019890019463 U KR2019890019463 U KR 2019890019463U KR 890019463 U KR890019463 U KR 890019463U KR 910013350 U KR910013350 U KR 910013350U
- Authority
- KR
- South Korea
- Prior art keywords
- real
- time domain
- division circuit
- domain division
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/10—Segmentation; Edge detection
- G06T7/11—Region-based segmentation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019890019463U KR920007326Y1 (en) | 1989-12-21 | 1989-12-21 | Region splitting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR2019890019463U KR920007326Y1 (en) | 1989-12-21 | 1989-12-21 | Region splitting circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910013350U true KR910013350U (en) | 1991-07-30 |
KR920007326Y1 KR920007326Y1 (en) | 1992-10-12 |
Family
ID=19293607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR2019890019463U KR920007326Y1 (en) | 1989-12-21 | 1989-12-21 | Region splitting circuit |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR920007326Y1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100480564B1 (en) * | 1997-08-26 | 2005-06-16 | 삼성전자주식회사 | Image segmentation and color synthesis circuit |
-
1989
- 1989-12-21 KR KR2019890019463U patent/KR920007326Y1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR920007326Y1 (en) | 1992-10-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
REGI | Registration of establishment | ||
FPAY | Annual fee payment |
Payment date: 20040922 Year of fee payment: 13 |
|
EXPY | Expiration of term |