KR910013265A - Word line connection method of semiconductor device - Google Patents

Word line connection method of semiconductor device Download PDF

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Publication number
KR910013265A
KR910013265A KR1019890020107A KR890020107A KR910013265A KR 910013265 A KR910013265 A KR 910013265A KR 1019890020107 A KR1019890020107 A KR 1019890020107A KR 890020107 A KR890020107 A KR 890020107A KR 910013265 A KR910013265 A KR 910013265A
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KR
South Korea
Prior art keywords
semiconductor device
word line
connection method
line connection
semiconductor memory
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Application number
KR1019890020107A
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Korean (ko)
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KR930001740B1 (en
Inventor
서동일
조수인
김영래
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019890020107A priority Critical patent/KR930001740B1/en
Publication of KR910013265A publication Critical patent/KR910013265A/en
Application granted granted Critical
Publication of KR930001740B1 publication Critical patent/KR930001740B1/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Abstract

내용 없음.No content.

Description

반도체 장치의 워드라인 접속방법Word line connection method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 실시예.2 is an embodiment of the present invention.

Claims (2)

워드라인의 시간지연을 줄이기 위해 다결정 실리콘과 금속을 접속하는 반도체 메모리 어레이에 있어서, 셀어레이 블록 사이에서 이루어지는 금속과 다결정 실리콘간의 접속을 소정 갯수의 워드라인마다 서로 엇갈리도록 함을 특징으로 하는 반도체 메모리 어레이.A semiconductor memory array which connects polycrystalline silicon and a metal to reduce the time delay of word lines, wherein the semiconductor memory array between the metal array and the polycrystalline silicon is staggered for each predetermined number of word lines. Array. 제1항에 있어서, 상기 소정 갯수의 워드라인이 상기 반도체 메모리 어레이내의 총 워드라인의 수가 2n개(m〉n≥0, m, n은 정수)의 갯수를 가짐을 특징으로 하는 반도체 메모리 어레이.The semiconductor memory array of claim 1, wherein the predetermined number of word lines has a total number of word lines in the semiconductor memory array of 2 n (m > n > 0, m and n are integers). . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890020107A 1989-12-29 1989-12-29 Wordline interface method of semiconductor device KR930001740B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890020107A KR930001740B1 (en) 1989-12-29 1989-12-29 Wordline interface method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020107A KR930001740B1 (en) 1989-12-29 1989-12-29 Wordline interface method of semiconductor device

Publications (2)

Publication Number Publication Date
KR910013265A true KR910013265A (en) 1991-08-08
KR930001740B1 KR930001740B1 (en) 1993-03-12

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ID=19294148

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020107A KR930001740B1 (en) 1989-12-29 1989-12-29 Wordline interface method of semiconductor device

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KR (1) KR930001740B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100512933B1 (en) * 2002-01-09 2005-09-07 삼성전자주식회사 Semiconductor memory device and block select signal generating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100512933B1 (en) * 2002-01-09 2005-09-07 삼성전자주식회사 Semiconductor memory device and block select signal generating method thereof

Also Published As

Publication number Publication date
KR930001740B1 (en) 1993-03-12

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