KR910010939A - Data Communication and Current Loop Matching Circuit in a Single Device - Google Patents

Data Communication and Current Loop Matching Circuit in a Single Device Download PDF

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Publication number
KR910010939A
KR910010939A KR1019890017068A KR890017068A KR910010939A KR 910010939 A KR910010939 A KR 910010939A KR 1019890017068 A KR1019890017068 A KR 1019890017068A KR 890017068 A KR890017068 A KR 890017068A KR 910010939 A KR910010939 A KR 910010939A
Authority
KR
South Korea
Prior art keywords
current
line
matching circuit
information
current loop
Prior art date
Application number
KR1019890017068A
Other languages
Korean (ko)
Other versions
KR920009155B1 (en
Inventor
권병재
Original Assignee
정용문
삼성전자 주식회사
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Publication date
Application filed by 정용문, 삼성전자 주식회사 filed Critical 정용문
Priority to KR1019890017068A priority Critical patent/KR920009155B1/en
Publication of KR910010939A publication Critical patent/KR910010939A/en
Application granted granted Critical
Publication of KR920009155B1 publication Critical patent/KR920009155B1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/02Details

Abstract

내용 없음No content

Description

데이타 통신 및 단일장치의 전류 루프 정합회로Data Communication and Current Loop Matching Circuit in a Single Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명과 RS 232C정합회로를 내장하여 데이타를 전송하는 시스템의 블럭도.2 is a block diagram of a system for transmitting data incorporating the present invention and an RS 232C matching circuit.

제3도 및 제4도는 본 발명의 상세회로도.3 and 4 are detailed circuit diagrams of the present invention.

Claims (1)

제1및 제2송수신기(10,20)간의 데이타 정보를 전송하기 위한 전류 루프 정합회로에 있어서, 제1-제4라인(L1-L4)과 , 상기 제1송수신기(10)로 부터 출력되는 제1전원 레벨의 직렬데이타 정보를 일정 전류흐름의 단속상태로 변환하는 제1수단과, 상기 제1수단의 출력 논리상태에 따라 스위칭 되어 제2전원 레벨의 전류가 상기 제1라인(L1)으로 유입되는 통로를 제어하는 제2수단과, 상기 제2라인(L1)에 제2전원 유입시에만 스위칭되어 제2라인(L2)으로 전류의 루프를 형성하는 제3수단과, 상기 제3수단의 전류루프 형성에 따른 단속정보를 제1전원레벨의 데이타 정보로 변환하여 상기 제2송수기(20)의 수신포트로 출력하는 제4수단과, 상기 제2송수기(20)의 제1전원레벨의 직렬데이타 정보를 전류흐름의 단속상태로 변환하는 제5수단과, 상기 제5수단의 출력상태에 따라 스위칭되어 제3라인(L3)의 제3전원레벨의 전류가 상기 제4라인(L4)으로 유입되는 통로를 제어하는 제6수단과, 상기 제4라인에 제3전원 유입시에만 스위칭되어 전류루프를 형성하는 제7수단과, 상기 제7수단의 전류루프 형성에 따른 단속정보를 제1전원 레벨의 데이타 정보로 변환하여 상기 제1송수신기(10)의 수신포트로 출력하는 제8수단으로 구성됨을 특징으로 하는 전류 루프 정합회로.In a current loop matching circuit for transmitting data information between the first and second transmitters 10 and 20, a first output from the first to fourth lines L1 to L4 and the first transmitter 10 is performed. A first means for converting serial data information of one power supply level into an intermittent state of a constant current flow, and switched according to an output logic state of the first means, so that a current of a second power supply level flows into the first line L1; Second means for controlling a passage to be formed, third means for switching only when the second power is introduced into the second line L1 to form a loop of current into the second line L2, and the current of the third means. Fourth means for converting intermittent information resulting from loop formation into data information of a first power supply level and outputting it to a receiving port of the second transmitter 20, and serial data of a first power supply level of the second transmitter 20; Fifth means for converting the information into the intermittent state of the current flow, and according to the output state of the fifth means. A sixth means for controlling a passage through which the current of the third power level of the third line L3 flows into the fourth line L4, and is switched only when the third power is introduced into the fourth line, thereby switching the current loop. And eighth means for converting the intermittent information according to the current loop formation of the seventh means into data information of the first power level and outputting the intermittent information to the receiving port of the first transmitter / receiver 10. A current loop matching circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890017068A 1989-11-23 1989-11-23 Current loop interface of data communication equipment and data terminal equipment KR920009155B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890017068A KR920009155B1 (en) 1989-11-23 1989-11-23 Current loop interface of data communication equipment and data terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890017068A KR920009155B1 (en) 1989-11-23 1989-11-23 Current loop interface of data communication equipment and data terminal equipment

Publications (2)

Publication Number Publication Date
KR910010939A true KR910010939A (en) 1991-06-29
KR920009155B1 KR920009155B1 (en) 1992-10-13

Family

ID=19291978

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890017068A KR920009155B1 (en) 1989-11-23 1989-11-23 Current loop interface of data communication equipment and data terminal equipment

Country Status (1)

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KR (1) KR920009155B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100535881C (en) 2007-04-29 2009-09-02 北京交通大学 Asynchronous serial communication method based on electric current loop

Also Published As

Publication number Publication date
KR920009155B1 (en) 1992-10-13

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