KR910010852A - Square wave phase delay circuit - Google Patents

Square wave phase delay circuit Download PDF

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Publication number
KR910010852A
KR910010852A KR1019890016632A KR890016632A KR910010852A KR 910010852 A KR910010852 A KR 910010852A KR 1019890016632 A KR1019890016632 A KR 1019890016632A KR 890016632 A KR890016632 A KR 890016632A KR 910010852 A KR910010852 A KR 910010852A
Authority
KR
South Korea
Prior art keywords
square wave
delay circuit
phase delay
charging
charge
Prior art date
Application number
KR1019890016632A
Other languages
Korean (ko)
Other versions
KR920004916B1 (en
Inventor
천병진
Original Assignee
강진구
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성전자 주식회사 filed Critical 강진구
Priority to KR1019890016632A priority Critical patent/KR920004916B1/en
Publication of KR910010852A publication Critical patent/KR910010852A/en
Application granted granted Critical
Publication of KR920004916B1 publication Critical patent/KR920004916B1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/86—Generating pulses by means of delay lines and not covered by the preceding subgroups
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof

Abstract

내용 없음No content

Description

구형파의 위상 지연회로Square wave phase delay circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 실시 회로도.3 is an implementation circuit diagram of the present invention.

제4도는 본 발명의 각부 파형도.4 is a waveform diagram of each part of the present invention.

제5도는 본 발명의 일실시 회로도.5 is a circuit diagram of one embodiment of the present invention.

Claims (3)

입력구형파 펄스의 전위레벨을 감지하여 전류흐름을 스위칭시키는 스위칭수단과, 상기 스위칭 수단의 전류 흐름에 따라 같은 기울기를 갖고 충방전 되어지는 충방전소자와, 상기 충방전소자의 충방전 전압을 기준전압과 비교시켜 위상 지연된 구형파 펄스를 출력시키는 비교 수단으로 구성된 구형파의 위상 지연 회로.The switching means for sensing the potential level of the input square wave pulse to switch the current flow, the charging and discharging element that is charged and discharged with the same slope according to the current flow of the switching means, and the charge and discharge voltage of the charge and discharge element reference voltage A square wave phase delay circuit comprising a comparison means for outputting a square wave pulse delayed in phase in comparison with. 제1항에 있어서, 구형파 입력은 같은 저항값을 갖고 연동되는 저항(R1)(R2) 을 통한 후 트랜지스터(Q1~Q4) 의 구동을 제어하여 충방전소자(3) 의 충방전 동작을 제어하게 구성하고 충방전 소자(3) 의 사다리꼴 전압 파형은 비교기(CP) 에서 기준 전압(Vref) 과 비교되어 위상지연된 구형파로 출력되게 구성시킨 구형파의 위상 지연 회로.The charging and discharging of the charge / discharge element 3 according to claim 1, wherein the square wave input controls the driving of the transistors Q 1 to Q 4 after the resistors R 1 and R 2 interlock with the same resistance value. Square wave phase delay circuit configured to control the operation and configured to output the trapezoidal voltage waveform of the charging and discharging element 3 as a phase delayed square wave compared to the reference voltage Vref in the comparator CP. 제2항에 있어서, 비교기(CP)의 기준전압(Vref) 을 설정하는 저항(R3)(R4)은 서로같은 저항값을 갖게 구성시킨 구형파의 위상 지연회로.The phase delay circuit of the square wave according to claim 2, wherein the resistors (R 3 ) (R 4 ) for setting the reference voltage (Vref) of the comparator (CP) have the same resistance values. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890016632A 1989-11-14 1989-11-14 Phase delay circuit of pulse KR920004916B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890016632A KR920004916B1 (en) 1989-11-14 1989-11-14 Phase delay circuit of pulse

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890016632A KR920004916B1 (en) 1989-11-14 1989-11-14 Phase delay circuit of pulse

Publications (2)

Publication Number Publication Date
KR910010852A true KR910010852A (en) 1991-06-29
KR920004916B1 KR920004916B1 (en) 1992-06-22

Family

ID=19291714

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890016632A KR920004916B1 (en) 1989-11-14 1989-11-14 Phase delay circuit of pulse

Country Status (1)

Country Link
KR (1) KR920004916B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100380158B1 (en) * 2000-12-29 2003-04-11 주식회사 하이닉스반도체 Delay circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100715852B1 (en) 2005-06-27 2007-05-11 삼성전자주식회사 Heating roller and image fixing apparatus using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100380158B1 (en) * 2000-12-29 2003-04-11 주식회사 하이닉스반도체 Delay circuit

Also Published As

Publication number Publication date
KR920004916B1 (en) 1992-06-22

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