KR910008944Y1 - Static type semiconductor memory device - Google Patents

Abstract

No content.

Description

Static type semiconductor memory device

1 is a block diagram showing the structure of a conventional semiconductor memory device.

FIG. 2 is a circuit diagram specifically showing each part of the semiconductor memory device shown in FIG.

Article 3 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 4 is a circuit diagram specifically showing each part of the semiconductor memory device shown in FIG.

5A to 5H are timing charts illustrating the operation of the semiconductor memory device according to an embodiment of the present invention.

6 is a block diagram showing the configuration of a semiconductor memory device according to another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: hang decoder 11: controller

20, 80: memory cell array 21-ii, 81-i: section

22-iii, 82-ii: memory cells 23-ii, 83-i: bit line load circuit

24-iii, 86-ii: column select gate circuit 27-ii, 87-i: partial sensing amplifier

28-i: block selection circuit 29-i: block detection amplifier

30, 89: latch circuit 88: main sensing amplifier

43, 93: flip-flops 44-47, 94-97: MOS transistor

41, 42, 91, 92: Inverter 24-11A, 29-1A, 87-1A: Drive part

27-11B, 29-1B, 87-1B: Load part

51, 52, 61, 101, 102: N channel driving transistor

53, 54, 63, 64, 103, 104: N channel switching transistor

55, 65, 105: N-channel current control transistor

56A, 56B, 66A, 66B, 106A, 106B: drive circuit

57, 58, 67, 111, 112: P channel MOS transistor

59A, 59B, 69A, 69B, 113A, 113B: Current Mirror Load Circuit

71, 72: NAND gate WLii: partial word line

[Industrial use]

The present invention relates to a semiconductor memory device composed of an insulated gate field effect transistor, such as a MOS transistor, and more particularly, to a static semiconductor memory device using a static cell as a memory cell.

[Traditional Technology and Problems]

In the semiconductor memory device, as the process technology is advanced and the memory capacity is increased, the load capacity of the data source to be driven by the memory cell is increased. This increase in the load capacity causes a decrease in the data reading speed. Therefore, in the conventional semiconductor memory device, the capacity to be driven by the memory cell must be reduced, so that the memory cell array is divided into a plurality of parts in order to speed up the data reading speed, and the partial data is provided for each part to provide the data within each part. BACKGROUND OF THE INVENTION [0002] A semiconductor memory device which drives only a corresponding partial data line in accordance with read data of a memory cell has been put into practical use.

FIG. 1 shows the structure of a conventional semiconductor memory device in which a merery cell array is divided into a plurality of parts, and it is assumed that the semiconductor memory device is a 1-bit read type to simplify the description. In the drawing, the memory cell array 80 is divided into a plurality of portions 81-1 to 81-n, and the static memory cells 82-11 in each portion 81-i (where i = 1 to n) are shown in FIG. 82-nn are arranged in a two-dimensional array shape with respect to each partial word line WLi (where i = 1 to n). Here, the semiconductor memory device will be described using the portion 81-1 as an example.

Each Mericell 52-li (where i = 1 to n) is a partial word line WL1 and a bit line pair divided for each part. Connected to each bit line Is connected to the bit line load circuit 83-1.

The word line WL is activated by a row decoder, not shown, and is disposed over the entire portion. The signal of this word line WL and the partial select signal SDi (where i = 1 to n) are supplied to the partial select gate circuit 88-i (where i-1 to n).

Here, the partial selection circuit SD1 output from the partial selection circuit 84-1 is activated only when the portion 81-1 is selected. Accordingly, only the partial word line WL1 of the selected portion 81-1 is activated based on the output signal of the partial select gate circuit 85-1. Then, data is read from all memory cells 82-1i (where i = 1 to n) connected to the activated partial word line WL1 in the selected portion 81-1, and the read signal corresponds to the read signal. Bit line pair Will be sent to.

The column select gate circuit 86-li (where i = 1 to n) is conductively controlled based on the column select signal CD, and bit line pairs belonging to the same portion 81-1. Signal is selected only by one bit by the column select gate circuit 86-li (where i = 1 to n). Will be sent to. This partial data pair The pair of signals passed down to are input to the partial detection amplifier 87-1, and each pair of data pairs. The partial sense amplifier 87-1 to which the signal of? Is input is selectively activated by the partial sense amplifier activation signal SSA1 output from the partial selection circuit 84-1. Here, the output of the inactivated partial sensing amplifier 87-1 is in a high impedance state.

The pair of signals output from the partial sense amplifier 87-1 is a main data line pair commonly wired throughout the portion. On the main data line Is input to the main sense amplifier 88 arranged in the chip in the vicinity of an output buffer (not shown). The pair of signals amplified by the main sense amplifier 88 is latched by the latch circuit 89 and then transmitted to the output buffer as read data DO.

FIG. 2 is a circuit diagram specifically showing each part of the conventional semiconductor memory device. In the drawing, the memory cells 82-11 include a flip-flop 93 and MOS transistors 94 and 95 functioning as transfer gates. Among them, the flip-flop 93 is composed by interlocking the input and output terminals of the two inverters (91, 92) consisting of a fixing box and a driving MOS transistor. The MOS transistor 94 is connected between one output terminal of the flip-flop 93 and the bit line BL-11, and the transistor 95 is a bit line of the other output terminal of the flip-flop 93. The gates of the two MOS transistors 94 and 95 are connected to the partial word line WL1 in the portion 81-11.

The pair of bit lines And partial data line pairs The column select gate circuit 86-11 connected therebetween is composed of two MOS transistors 96 and 97 to which a column select signal CD is supplied to the gate.

The partial sensing amplifier 87-1, referred to as a current mirror parallel sensing amplifier, is divided into a driving unit 87-1A and a load unit 87-1B, and the driving unit 87-1A is a partial data. Line pair The currents of the driving transistors 101 and 102 of the N channel and the switching transistors 103 and 104 of the N channel to which the partial sense amplifier activation signal SSA1 is supplied to the gate are supplied to the gate, respectively. It consists of a drive circuit 106A composed of the control transistor 105 and a drive circuit 106B identical to the structure of the drive circuit 106A. Similarly, the load section 87-15 is composed of two current mirror type load circuits 113A and 113B each consisting of two P-channel MOS transistors 111 and 112. Here, in each of the partial detection amplifiers 87-1, only the driving unit 87-1A is provided corresponding to each partial data line, and only one unit is installed in common for all the partial sensing amplifiers for the load unit 87-1B. It is.

When using this type of partial sense amplifier, the main data line pair of the main unit as the main data line pair. In addition, main data pair for reference Also installed.

In the conventional semiconductor memory device, the memory cell array is divided into a plurality of parts, and when reading data, one part is selectively activated to read the selector, and the read signal is partially sensed amplifier 87-i; Where i = 1 to n) The main sense amplifier 88 is amplified and converted to a CMOS amplitude level, and then latched by the latch circuit 89.

In such a semiconductor memory device, a partial data line pair Since each part is divided, each bit line pair Column select gate circuit 86-ii where i = 1 to n) Compared to the direct transmission to the direct current, the load capacity required to be driven directly by the small cell having a small current driving capability becomes smaller. Therefore, the data reading speed can be made to a certain speed.

However, as the memory capacity of the semiconductor memory device is further increased, the number of parts increases and the main data line In addition to the increase in wiring capacity or load capacity, the pair of main data lines in the partial sense amplifier 87-1 of FIG. The total sum of the drain junction capacities of the switching transistors 103 and 104 of the N channel connected to is increased because the number of parts increases. Thus, the load capacity that the selected partial sense amplifier 87-1 must drive is increased. Therefore, main data line pair There is a drawback that the speed of signal change is slowed down and thus the data read speed is slowed down.

As a countermeasure, it is conceivable to increase the transistor size of the driving transistors 101 and 102 in the partial sense amplifier 87-1, but it is necessary to increase the transistor size of the switching transistors 103 and 104 accordingly. The drain junction capacity is further increased. Therefore, even if the transistor size in the partial sense amplifier 87-1 is increased, the data read speed cannot be increased. In addition, as the transistor size increases, a problem arises in that the power consumption of the partial sense amplifier 87-1 increases. As described above, in the conventional static type semiconductor memory device, there is a drawback that the data reading speed is slowed down as the storage capacity is increased.

[Purpose of designation]

The present invention has been devised in view of the above circumstances, and its object is to provide a static type semiconductor memory device capable of speeding up the reading speed of data even if the capacity is increased.

[Composition of design]

The static semiconductor memory device of the present invention for achieving the above object is divided into a plurality of blocks each divided into a plurality of parts, a plurality of memory cell array in which memory cells are arranged in a matrix form, and the plurality of A plurality of parts respectively installed corresponding to one of the plurality of parts to receive the read data and amplify the read data first when reading the data from the selected one of the selected plurality of memory cells belonging to the corresponding part; A plurality of block sensing amplification means, each block corresponding to one of the plurality of blocks, the second amplifying the first amplified data output from the corresponding partial sensing amplification means belonging to the corresponding block; An amplifying means and 2 output from the block detecting amplifying means. In a static type semiconductor memory device having a latch means for latching amplified data, the sensing characteristic of the partial sensing amplification means is higher than that of the block sensing amplification means, and the current driving of the block sensing amplifying means is performed. The characteristic is larger than the current driving characteristic of the partial sense amplifying means.

[Action]

In the static type semiconductor memory device of the present invention configured as described above, the output of the partial sensing intermediate amplifier installed in each part is input to the block sensing amplifier provided in units of blocks, and the output of the block sensing amplifier is wired over all blocks. The data line is supplied to latch the data of this main data line with a latch circuit.

By distributing the block detection amplifiers of the second stage as described above, the output capacity of the first stage partial sensing amplifier is reduced, and the number of block detection amplifiers connected to the main data lines is reduced, thereby reducing the total capacity of the main data lines. This can speed up the reading speed of

EXAMPLE

Hereinafter, each embodiment of the present invention will be described in detail with reference to the exemplary drawings. FIG. 3 shows a configuration of a semiconductor memory device according to an embodiment of the present invention. In the drawing, the row decoder 10 according to an input row address is shown. The main word line WL selected from among the plurality of word lines is activated. Here, the selected main word line WL is at a low level in an active state. On the other hand, according to the input column advice, the controller 11 connects the column selection signal CD, the partial selection signal SS, and the block selection signal BS to the selection gate circuit 26-iii and the partial selection circuit 24-. ii) and block selection circuits 28-i, respectively.

In the memory cell array 20, the main word line WL is divided into a plurality of blocks in the extending direction, and each of the blocks has a plurality of portions 21- along the extending direction outside the main word line WL. ii). In each part 21-ii, the static memory cells are arranged in a two-dimensional array shape, and each memory cell in each part, for example, the memory cells 22-111 in the part 21-11, is for each part. Divided partial word line (WLLL) and bit line pair Is connected to. Moreover, each bit line in the part 21-11 Is connected to the bit line load circuit 23-11.

The partial select signal SD, which is an active low level output from the signal of the main word line WL and the partial select circuit 24-11, at the input terminal of the partial gate circuit of each portion, for example, the partial select gate circuit 25-11. -11) is supplied, and the partial selection signal SD-11 is activated according to the signal SS only when the corresponding portion is selected, and the partial selection gate circuit is activated in accordance with the activation of the partial selection signal SD-11. The output of (25-11) and the partial word line wL11 belonging to the selected portion are activated.

Then, data is read from all the memory cells 22-11i connected to the couple word line WL11 in the selected portion, and the bit line pair corresponding to the read signal is read. Will be sent to.

Activation of the column select gate circuit (CSG) 26-11li is conducted and controlled in accordance with the soft select signal (CD) from the controller 11, and bit line pairs belonging to the same portion. The signal of? Is selected only by one bit by the column select gate circuit 26-11i, which is electrically controlled based on the column select signal CD, and the pair of partial data lines provided corresponding to each part. Will be sent to.

This partial data line pair The partial sense amplifier 27-11 to which the signal is supplied is selectively activated according to the partial sense amplifier activation signal SSA11 output from the partial selection circuit 2B-11. Thus, partial data line pairs The signal of is amplified by the partial sense amplifier 27-11 and then transmitted to the block data line pair provided for each block.

For example, block data line pairs Is input to the block detection amplifier 27-11 which is selectively activated by the block detection amplifier activation signal BSA1 output from the block selection circuit 28-1 according to the block selection signal BS. The block sensing amplifier 29-1 outputs complementary data by further amplifying the signal amplified by the partial sensing amplifier 27-11. The output data of the block sensing amplifier 29-1 Primary data line pairs commonly wired across all blocks Will be sent to. On the main data line Data is latched by the latch circuit 30 disposed near the output buffer (not shown) in the memory chip and transferred to the output buffer as read data DO.

FIG. 4 is a circuit diagram showing each part of the semiconductor memory device shown in FIG. 3 in detail. The partial selection gate circuit 25-11 is a signal transmitted from the row decoder 10 to the main word line WL and The partial selection circuit SD-11 outputted from the partial selection circuit 24-11 is configured as a NOR gate to which the partial selection circuit SD-11 is input. As in the conventional semiconductor memory device, the meriscell 22-111 has a flip-flop 43 and MOS transistors 44 and 45 which can be formed as transfer gates, respectively, of which the flip-flop 43 has high resistance and drive. The input / output terminals of two inverters 41 and 42 made of MOS transistors for interconnection are connected to each other. The MOS transistor 44 is connected between the output connection point of the inverter 41 and the bit line BL-111, and the MOS transistor 45 is connected to the output connection point and the bit line of the inverter 42. The gates of the two MOS transistors 44 and 45 are connected to the partial word lines WL11 in the portions thereof.

The pair of bit lines And partial data line pairs The column select gate circuits 26-11 connected therebetween are composed of two N-channel NOS transistors 46 and 47 supplied with a column select signal CD to the gate.

In addition, the partial sensing amplifier 27-11, which is called a current mirror parallel sensing amplifier, is divided into a driving unit 27-11A and a load unit 27-11B, of which the driving unit 27-11A is a partial data line pair. Switching transistors for the N channel supplied with the partial sensing amplifier activation signal SSA11 outputted from the driving transistors 51 and 52 and the partial selection circuit 24-11 of the N channel supplied with the respective signals to the gate. And two driving circuits 56A and 56B which are composed of (53, 54) and an N-channel current-carrying transistor 55. Here, the drive part 27-11A is provided with the drive part 29-1A mentioned later. Here, the drive part 27-11A has the same structure as the drive part 29-1A mentioned later.

The load section 17-11B has two current mirror type load circuits 59A and 59B each consisting of two P-channel MOS transistors 57 and 58. Here, in each of the partial sensing amplifiers 27-11, only the driving section 27-11A is provided corresponding to each partial data line pair, and for the load section 27-11B, only one common to all the partial sensing amplifiers is provided. It is installed.

In the case of using the partial sense layer attenuation 27-11 of this type, a block data line pair Block data line pair for reference Is installed. The driving transistor 51 on the side of the driving circuit 56A in the driving unit 27-11A of the partial sensing amplifier 27-11 has an original block data. Connected to the drain data block data line of the driving transistor 52 On the other hand, the drain of the driving transistor 51 on the driving circuit 56B side is connected to the reference block data block BDLR-1, and the drain of the driving transistor 52 is the original block data. It is connected to the option BDL-1, respectively.

The block sensing amplifier 29-1, also referred to as a current mirror parallel sensing amplifier, is also divided into a driving unit 29-1A and a load unit 29-1B, of which the driving unit 29-1A is a block data line pair. N-channel switching in which the N-channel driving transistors 61 and 62 and the block detection amplifier activation signal BSA1 output from the block selection circuit 28-1 to which the respective signals are supplied to the gate are supplied to the gate, respectively. Two driving circuits 66A and 66B are formed of the transistors 63 and 64 and the N-channel current-carrying transistor 65. Here, the drive part 29-1A is comprised similarly to the drive part 27-11A mentioned above.

Similarly to the difference between the load portions 27-11B, the load portion 29-1B includes two current mirror type load circuits 69A and 69B each consisting of two P-channel MOS transistors 67 and 68, respectively. Here, in each block detection amplifier 29-1, only the drive unit 29-1A is provided corresponding to each block data line pair, and only one unit is installed in common for all the block detection amplifiers for the load unit 29-1B. It is.

When using this type of block detection amplifier. Primary data line pair In addition, main data pair for reference Is installed. The drain of the switching transistor 63 on the inside and outside of the driving unit 29-1A and the driving circuit 66A of the block sensing amplifier 29-1 is an original main data line pair main data line. Is connected to the drain of the switching transistor 64 for reference. While the drain of the switching transistor 63 on the driving circuit 66B side is connected to the reference main data line MDLR, the drain of the switching transistor 64 is the main data line of the present fo. It is connected to (MDL).

The latch circuit 30 is composed of two NAND gates 71 and 72 and a main data line pair. It consists of flip-flops into which data is input.

Next, the operation of the semiconductor memory device that is subjected to the above described operation will be described using the timing chart shown in FIGS. 5A to 5H.

First, when the address is changed as shown in FIG. 5A and a new address is inputted, one word as shown in FIG. 5B by the output of the row decoder 10 when the row address is supplied to the row decoder 10. The line WL becomes active ("O" level), where the crawler 11 receives the received open-dress signal to select a portion belonging to one block, for example, the portion 21-11 of the block 1. In response to the partial selection signal SS, the partial selection circuit 24-11 activates the partial selection signal SD-11 as shown in FIG. 5C ("0" level). The signal of the partial selection signal SD-11 and the word line WL is inputted to the partial selection gate circuit 25-11. The partial word line is output in accordance with the output of the partial selection gate circuit 25-11. (WL11) is activated ("1" level) as shown in Fig. 5d. Here, the partial word line WL11 to be activated is only in one portion 21-11 of one block.

When the partial word line WL11 is activated, the memory cells 22-lli connected to the partial word line WL11 in the portion 21-11 are simultaneously selected and run in parallel from these memory cells 22-11i. The data will be read. Therefore, when reading data from the memory cells 22-11i, each bit line pair as shown in Fig. 5E. There is a subtle difference in the potential of.

In addition, according to the input column address at this time, the column select signal CD is output from the controller 11 to the column select gate circuit (CSC) 26-11i to activate the column select gate circuit 26-11i. Accordingly, bit line pairs connected to the column select gate circuits 25-11i. As shown in Fig. 5f, the signal of Will be sent to. Furthermore, one partial sense amplifier 27-11 is activated by the partial sense amplifier activation signal SSA11 from the partial selection circuit 24-11 to perform the partial data line pairing. The amplified signal is amplified by the block data line pair provided in the block as shown in FIG. Will be sent to. Further, the block selection circuit 28-1 is activated in accordance with the block selection signal BS output from the controller 11 in accordance with the input string address at this time, and thus the block detection amplifier activation signal from the block selection circuit 28-1. The BSA1 is outputted, and the block sensing amplifier 29-1 is activated in accordance with the block sensing amplifier activation signal BSA1. As a result, block data line pairs Signal is amplified by the block detection amplifier 29-1, and as shown in FIG. Will be sent to. Then, the main data line pair Is latched by the latch circuit 30, and the latch data is output as the read data DO.

As described above, in the semiconductor memory device of the above embodiment, the output of the partial sense amplifier 37-11 as the first sense amplifier provided in each section is input to the block sense amplifier 29-1 as the second sense amplifier provided in units of blocks. Main data line pairs wired to the output of the block sense amplifier 29-1 over all blocks To the main data line pair It is to latch the data of the latch circuit 30. Although the above embodiment has been described with reference to portions 21-11, it is applicable to other portions of the same block as well as portions of other blocks. Further, in the above embodiment, the memory cell array is divided into n blocks each divided into n parts, but the number of blocks to be divided may be different from the number of parts to be divided.

Here, the output terminal of each partial sense amplifier 27-ii is a block data line pair. Block data line pairs because they are commonly connected to the output terminals of some other sense amplifiers belonging to the same block. The number of the transistors 51 and 52 in each of the partial sense amplifiers 27-ii connected to is smaller than before. Thus, block data line pairs The total of the connection capacities connected to is sufficiently small. In addition, block data line pairs Wiring length itself Main data line pair Since it is shorter than that, the wiring capacity is also reduced.

Therefore, the output load capacity of each of the partial sense amplifiers 27-ii becomes significantly smaller than the output load capacity of the partial sense amplifiers of the conventional semiconductor memory device. It can be changed at high speed. Each block data line pair The load capacity of the block detection amplifier 29i that amplifies the signal is larger than that of the main detection amplifier of the conventional semiconductor memory device. However, the load capacity of the block sensing amplifier 29-i is the main data line pair. Wiring capacity and main data line pair The sum of the drain junction capacities of the transistors 63 and 64 in the block sense amplifier 29-i connected to the sum is obtained. However, this capacitance becomes smaller as the number of sensing amplifiers is smaller than that of the partial sensing amplifier of the conventional semiconductor memory device.

In the static semiconductor memory device of this embodiment, the output load capacity of each of the partial sense amplifiers 27-ii of the sense amplifier of the first stage and the block sense amplifiers 29-i which are the sense amplifiers of the second stage are shifted to one side. Since it is possible to prevent them from being hit, the sum of the signal delay times in each pair of data lines can be made smaller than that of the conventional semiconductor memory device. As a result, high-speed reading of data can be realized.

In addition, in this embodiment, since the output load of the partial sensing amplifier 27-ii is small, it is not necessary to give the partial sensing amplifier 27-ii a large current driving capability. Therefore, as the partial sensing amplifier 27-ii, as shown in FIG. 4, the driving transistors 51 and 52 can be arranged on the output side to be designed to have high sensitivity. That is, the partial sensing amplifier 27-ii can be designed with sensitivity priority. In contrast, in the conventional partial sensing amplifier of the semiconductor memory device shown in FIG. 2, it is necessary to arrange the switching transistors 103 and 104 on the output side to have a large current driving capability.

Further, for the block detection amplifier 29-i, a block data line pair Since the amplitude of the signal in the circuit is somewhat large, the relatively large load capacity can be sufficiently driven. As the block sensing amplifier 29-i, as shown in FIG. By arranging, the current driving capability can be designed to have a large characteristic. In other words, the block detection amplifier 29-i can be designed with a driving force priority.

As described above, in the semiconductor memory device of the present invention, as in the conventional semiconductor memory device, the sensing amplifier has a two-stage configuration. However, let this be a three-stage configuration, and the main data line pair It is conceivable to further amplify the data by the sense amplifier. However, in such a scheme, the total current flowing to the sense amplifier increases or the transistors constituting the sense amplifier must be made smaller under the condition that the total current is constant. Since the total current is limited in the memory IC, the sense amplifier is limited. In order to achieve a three-stage configuration, only the transistor size is reduced. Therefore, the sensing amplifier has a two-stage configuration, which is at a high speed toward the semiconductor memory device of the present invention which appropriately distributes each output capacity. In general, the direct current amplification factor of the sense amplifier of the current mirror parallel sense amplifier type is about 15. Therefore, partial data line pair at the time of data reading Even if the potential difference between them is about 0.1v, the main data line pair The potential difference between them can be made large enough as a CMOS level.

In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the summary. For example, in the semiconductor memory device of the embodiment, a pair of bit lines belonging to the same portion Although only one bit of the signal of? Is selected by the column select gate circuit 26-iii, and the data finally outputted is described as one bit, this is a bit line pair belonging to the same part. M bits may be selected by the m column select gate circuits 26-iii, and finally m bits of data may be output in parallel. In this case, m pairs of partial data lines Is provided, so that the partial sense amplifiers 27-ii and the block data line pairs are respectively provided for each of these partial data line pairs. Block detection amplifier (29-i), main data line pair And the latch circuit 30, etc. need to be provided.

In the above embodiment, a case has been described in which the memory cell 22-iii uses a high resistance load type. However, the flip-flop 43 is a CMOS type using a P-channel MOS transistor and an N-channel MOS transistor. You may use one. Furthermore, in the above embodiment, a so-called word line redundancy semiconductor memory device in which partial word lines and word lines are provided has been described. However, as shown in FIG. 6, the memory cell array is divided into a plurality of blocks instead of the redundancy method. In addition, the word memory multiple division type semiconductor memory device, such as a row decoder for each block, can be implemented.

In this case, the basic operation is the same as that of the first embodiment. However, if the present invention is implemented in a word line duplex semiconductor memory device capable of increasing the number of divisions without causing such an increase in chip size, the effect becomes even greater.

As described above, according to the present invention, it is possible to provide a static semiconductor memory device capable of speeding up the reading speed of data even when the capacity is increased.

Claims (10)

A plurality of memory cell arrays 20 which are divided into a plurality of blocks each divided into a plurality of parts, in which a plurality of merery cells 22-111 are arranged in a matrix form, and corresponding to the plurality of parts, respectively. A plurality of partial sensing amplification means 27-11 to be provided to receive the read data and to amplify the read data first when reading data from one selected memory cell among the selected plurality of merolicells belonging to the corresponding portion; 27-nn) The first amplified data output from the corresponding partial sense amplification means 27-11 to 27-nn respectively provided corresponding to one of the plurality of blocks and belonging to the corresponding block is second. The second amplified data output from the plurality of block detection amplification means 29-1 to 29-n and the block detection amplification means 29-1 to 29-n are amplified. In the static semiconductor memory device having the latch means 30, the sensing characteristics of the partial sense amplification means 27-11 to 37-nn are the block sense amplification means 29-1 to 29-n. Static current characteristics higher than the detection characteristics, and the current driving characteristics of the block detection amplifying means 29-1 to 39-n are larger than the current driving characteristics of the partial image amplifying means 27-11 to 27-nn. Type semiconductor memory device. The apparatus of claim 1, further comprising: row decoding means (10) for selecting one main word line among a plurality of main word lines (WL) in accordance with an input row address, wherein each part includes the plurality of main word lines The plurality of partial word lines WL11 corresponding to (WL), a plurality of memory cells 22-111 connected to the plurality of partial words WL11 and arranged in a matrix form, and the activation of the selected Merolicell. And a partial selection gate means (25-11) for connecting the partial word lines to activate the partial word lines corresponding to the selected main word lines. The partial word line of claim 1, wherein the activated partial word line is connected to the selected memory cell, and one partial word line of a plurality of partial word lines is selected through the portion belonging to the corresponding block according to an input row address. And a plurality of row decoding means (10) which are respectively provided in correspondence with one of the plurality of blocks for giving. 2. The apparatus of claim 1, wherein the m portion detecting amplifier means is provided in each of the portions to first amplify the data read out from the m memory cell, and the m block detecting amplifier means is provided in each of the blocks. The k block detection amplification means amplifies the data amplified first by the k partial detection amplification means of the m partial detection amplification means for the second time, and the m latch means is installed in each of the blocks so that the k latch means of the m latch means is provided. And the second amplified data outputted from the k-block detection amplifying means is latched. 2. The control means (11) according to claim 1, wherein the control means (11) selectively generates a column selection signal (CD) in accordance with an input column address, and corresponds to both of the selected memory cells, wherein the corresponding portions and the corresponding partial sense amplification amplifiers. Multiple bit line pairs in the means A plurality of column selections respectively provided between one pair of bit lines to output read data from a memory cell selected according to the column selection signal CD from the control means 11 to the corresponding partial sense amplification means; A static semiconductor memory device characterized by further comprising gate means (26-111 to 26-nnn). 6. The control means (11) according to claim 5, wherein the control means (11) outputs first activation signals (SSA11 to SSAnn) to the plurality of partial sense amplifier means (27-11 to 27-nn), respectively. Means for selectively generating the first and second activation signals in accordance with the input string address to output second activation signals BSA1 to SSAnn to 29-1 to 29-n, respectively. Each of the partial sensing amplification means 27-11 to 27-nn is selectively activated according to the first activation signals SSA11 to SSAnn, and each of the block sensing amplification means 29-1 to 39-n And a static type semiconductor memory device which is selectively activated according to the second activation signals BSA1 to BSAn. 7. The apparatus as claimed in claim 6, wherein each of the partial sensing amplification means includes a drive portion 27-11A which is provided separately in each of the partial sensing amplification means belonging to a corresponding portion, and the entire partial sensing amplification means belonging to the corresponding portion. A static type semiconductor memory device, characterized in that the current mirror parallel sensing amplifier consisting of a load unit (27-11B) is installed in common. 10. The block data line pair as claimed in claim 7, wherein the driving unit (27-11A) is provided with a block data line pair as data read from the memory cells (22-111) is supplied to a gate. Data line pairs A first pair of transistors 51 and 52 driving one of the transistors and a pair of transistors 51 and 52 of the first pair, respectively, and the first activation signal SSA11 is jointly supplied to a gate. Data read from the first transistor 55 memory cells 22-111 that are commonly connected to the second pair of transistors 53 and 54 and the second pair of transistors 53 and 54 to control current. The block data line pairs as the is supplied to the gate And the reference block data line pair A fourth pair of transistors 51 and 52 driving the other one of the transistors, and a fourth pair of transistors 51 and 52 connected to the three pairs of transistors 51 and 52, respectively, to which the first activation signal SSA11 is commonly supplied to a gate; And a second transistor (55) connected in common to the pair of transistors (53, 54) and the fourth pair of transistors (53, 54) to drive a current. 7. The apparatus according to claim 6, wherein each of the block sensing amplifying means includes a drive section 29-1A, which is provided separately in each of the block sensing amplifying means belonging to the corresponding block, and the entire block sensing amplifying means belonging to the corresponding block. Static type semiconductor memory device, characterized in that the current mirror parallel sensing amplifier consisting of a load unit (29-1B) installed in common. 10. The pair of main data lines of claim 9, wherein the driving unit 29-1A is supplied with the second activation signal BSA1 to a gate in common. Data line pairs The first pair of transistors 63 and 64 for driving one of the first and second pairs of transistors 63 and 64, respectively, and the data outputted from the partial sense amplification means 27-11 to the gate; Is connected to the second pair of transistors 61 and 62 to which the second pair is supplied, the first transistor 65 to control the current in common with the second pair of transistors 61 and 62, and the second activation signal BSA1. The main data line pair as is supplied to the gate in common And the reference main data line pair The third pair of transistors 63 and 64 and the third pair of transistors 63 and 64 respectively driving the other one, and the data output from the partial sensing amplification means 27-11 to a gate; And a fourth transistor (61, 62), to which the second pair of transistors (61, 62) are commonly supplied, and a second transistor (65) characterized by comprising a second transistor (65) by driving a current. Memory.