KR910008823Y1 - Programmable controller - Google Patents

Abstract

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Description

Programmable Logic Controllers (PLCs)

1 is a schematic overall circuit block diagram of a PLC according to the present invention.

2 is a flow chart of input and output data for explaining the present invention.

3 is an input drive circuit diagram applied to the present invention.

4 is an output drive circuit diagram applied to the present invention.

5 is a relationship with the expansion unit in which the present invention is implemented.

* Explanation of symbols for the main parts of the drawings

10: central control unit 11: peripheral interface

12: reset circuit 13: supervisory control unit

14: oscillation and division circuit 15: RAM

16: EP-ROM 17, 18: input and output interface

19, 19 ', 19 ": address decoder 20, 20', 20": compensation circuit (adder)

21: NAND Gate 22: Bidirectional Bus Transceiver

23, 24, 25: input and output data buffer 26-33: output driver circuit

34-41, 42-49: Input driver circuit 50, 51, 52: Signal amplifier

53: RC filter circuit 54: bridge rectifier circuit

55: input terminal block 56: output circuit

57: triac drive circuit 58: output terminal block

100: basic unit 200, n: expansion unit

R1-R9: resistance LED1-LED5: light emitting element

PT1-PT3: Photocoupler C1-C7: Condenser

D1-D2: Diode PD1: Phototriac

TR1AC: Triacs Ry1, Ry1a: Relays and Contacts

X1-X16: Input terminal Y1-Y8: Output terminal

COM: Common terminal

The present invention relates to a programmable logic controller in which an output load such as a motor, a solenoid valve, and the like is sequentially controlled according to a programmed sequence, and includes 16 input driver circuits for reading input data, and their input data are centered. There are eight output driver circuits that are processed by the controller and output sequentially, and the own input and output decoders are executed by signals commanded from the central controller. The goal is to provide a programmable logic controller that allows the output direction to be determined and allows connection in a pre-location manner without restriction in order of expansion.

In general, a sequence control circuit for an automation system is a control circuit which performs control of each step sequentially according to a predetermined order such as confirming completion of a control operation and selecting the next operation according to the result. Composed of relay coil and contacts of various switches, this means that if the user changes the circuit according to the arrangement and combination of various switches for the installation method, new circuit wiring should be performed to meet the proper conditions. Inconvenient hassle is followed, and even if the circuit wiring as described above, there was a lot of difficulties in the actual use because of the lack of circuit maintenance, reliability and precision in the long term.

Recently, a large number of programmable controllers formed in one box type have been introduced. Looking at common functional means, various switches input signals from each other through the central processing unit and the EP-ROM. And the RAM to operate the motor, cylinder and relay on the output side according to the program and information input from the keyboard.

In addition, it was possible to use one programmable controller that accommodated the number of points of input and output contact devices relatively, and to use it when it is applied to a small scale of the automatic control system, but when the control system is large, The same programmable logic controller has been installed and used in a comprehensive way. In order to facilitate the exchange of data information between them, each of the delimiter information must be included, and only the basic unit can be used depending on the control situation of the control object. In addition, unique address should be set in extension unit.

Therefore, it is necessary to be aware of the unique numbers of all the expansion units at all times because it sets the delimiter information about itself of the basic unit in the physical switching operation at the time of expansion or as the designated address of the central control unit in the basic unit. There was a lot of uncomfortable problems in the configuration.

Therefore, the present invention was conceived in view of the above, and includes an address decoder in one basic unit, but after receiving an address signal from the central control unit and decoding the address, it is determined that it is its own address. Decode the output ports accordingly, and if it is not your address, the function value set in the unit setting function unit returns to the output by addition (compensation) according to the selected mode, so that the next extended unit can be designated sequentially. Specifically, it includes 16 input driver circuits that can use alternating current or direct current depending on the control system and user requirements. The output points include eight output driver circuits classified as relays, transistors, or phototriacs (SSRs). Automatically by selecting and applying in a single or multiple configuration as appropriate The aim is that the rational induces the control unit of the system.

The configuration of the present invention for achieving this in more detail with reference to the accompanying drawings as follows.

FIG. 1 is an overall circuit block diagram according to the present invention, and basically includes a central controller 10 operation state sensing unit 13, a reset circuit 12, and an oscillation clock divider circuit 14. As shown in FIG. (10) Peripheral device interface (11) for accommodating external peripherals at its center, EP-ROM (16) containing self-executing program for controlling input and output data by central controller 10, and data of control system RAM 15, which temporarily stores input information, and input and output interfaces 17 and 18 are connected to mutual addresses, data, and control buses, and the input and output interfaces 17 have input and output data flows. The bidirectional bus transceiver 22 for changing the direction is connected to transmit and receive data of the central controller 10 and input / output data in one byte (8 bits), and decoded from the decoder 19. As a signal source The logic signal of the NAND gate 21 is connected to be applied to the (G) terminal of the bidirectional bus transceiver 22, and the control terminal DIR is connected to the input and output signal according to the control signal provided from the central controller 10. An IORD and an IOWR that connect the data flow direction on the output side are popularly connected, and the other input and output interface 18 has a decoder unit connected to an addition circuit 20 for an expansion unit. 19 is connected to the address control bus, and the input and output data buffers 23-25 are provided on the output side of the decoder 19 on the other side, and the address (A0-A6) data (D0-D7). Each of the input data buffers 24 and 25 is connected to each of the signal amplifiers 50 and 51, which is composed of eight drive circuits (not shown) connected to Darlington. The signal amplifier 50 has the same configuration as those of FIGS. 3A and 3B shown in FIG. An input driver circuit 34 for receiving only an AC contact or a collecting contact input signal is connected, and accommodates eight input driver circuits 34-41 configured in the same way as the input driver circuit 34 thereof, and another signal amplifier. (51) also has the same configuration as described above, and the input driver circuits 34-41 and 42-49 of all one point for reading the entire input data are concluded, and the input side signal is output to the output side data buffer 23. Signal amplifiers 52, such as amplifiers 50 and 51, enable the drive points such as FIGS. 4A, 4B, and 4C shown in FIG. 4 to be selectively configured as relay triacs or transistors. Four identical output driver circuits 26-33 are connected.

One of the sixteen input driver circuits 34-4 and 42-49 applied to the above is provided with one DC input signal source X1 as shown in FIGS. 3A and 3B. The light emitting element LED1 and the photocoupler PT1 are connected to the input terminal block 73 to be applied, and an RC filter circuit 53 made of a resistor R4-R6 and a capacitor C4 is connected to the output side aviator thereof. The input signal terminal X1 and the common terminal COM of the input terminal block 73 to which one AC contact signal is applied as shown in FIG. 3B are bridged through the resistors R7 and R8 and the capacitor C5. A rectifier circuit 54 is connected, and a photocoupler PT2 having a resistor R9 in parallel is connected to both positive and negative ends thereof, and an emitter terminal of the output side thereof is connected to a light emitting device LED2 having one side grounded. A resistor R10 connected in series is connected, and an RC filter circuit 53 composed of resistors R11-R13 and a capacitor C6 is connected.

In addition, one output driver circuit 26 of the eight output driver circuits 26 to 33 applied above is provided with a direct current of 24V at the output of the signal amplifier 52 as shown in FIGS. 4A, 4B, and 4C. The relay Ry1 and the light emitting device LED3 driven by are connected to each other, and the contact point Ry1a of the relay Ry1 is connected to the capacitor R14 and the capacitor C7.

As another example, the light emitting device LED4 driven by DC 5V, the resistor R15 and the photocoupler PT3 are sequentially connected to the output side of the signal amplifier 52, and the meter is connected to the resistor R16 and the transistor ( The output drive circuit 26 formed by connecting Q1) and the output circuit 56 composed of the diodes D1 and D2 can be applied.

As another example, the resistors R18 and R19, the capacitors C8 and the triacs TRIAC are applied to both ends of the output amplifier of the signal amplifier 52, on which the phototricoupler PD1 is applied instead of the photocoupler PT3. The output drive circuit 26 formed by connecting the triac driving circuit 57 consisting of < RTI ID = 0.0 >

Reference numerals Y1-Y8 denote output terminals, 58 denote output terminal blocks, and X1-X16 denote input terminals.

The present invention, which operates according to the systematic signal flow as described above, will be described with reference to FIG. 1 to FIG.

When the AC power is first supplied to use the programmable logic controller of the present invention, the power is supplied to the DC driving power required for each circuit part including the reset circuit 12 through a rectifier (not shown).

In this case, each circuit section is reset to the initial state by the reset circuit, and the oscillated frequency is supplied to the central control unit as a clock-divided signal, so that the central control unit 10 according to the EP-ROM module containing the user program. Will start the program.

That is, since each circuit is reset to the initial state for using the programmable logic controller, the contact states of various switches and sensors connected to the input terminal block 55 can be set to the respective input driver circuits (34-41), (42-49). A program that will be sensed by) and operate a motor, cylinder, relay, etc. connected to the output terminal block 58 under the control of the central control unit 10 is executed.

In order to determine whether to read or output the input data, the central control unit 10 that executes such a program must first determine the direction of the direction of the bidirectional bus transceiver 22.

In other words, the IORD of the control signal sent from the central control unit 10 is applied to the address decoder unit 19 and simultaneously developed into a high signal by the NAND gate 21 to generate the high signal. This signal causes the bidirectional bus transceiver 22 to open its gate element toward the input and output interface 17 to receive input data. At this time, each switch contact signal input from the input terminal block 55 is input driver circuit (34-41), (42-49) and signal amplifiers (50), (51) and input data buffer (24), The data signal is formed as 8 bits of a data bus that is designated one channel by 16 points in units of 25, and the data signal is connected to the central controller 10 through the bidirectional bus transceiver 22 and the input / output interface 17. The input is stored in the system ROM and the RAM 15.

That is, when each switch contact signal input from the input terminal block 73 is applied to each of the input driver circuits 34-41 and 42-49 by this process, the input driver circuit 34 has a first effect. As shown in FIG. 2 and FIG. 3, when receiving as a DC input contact, it short-circuits the contact terminal (X1) and the common terminal (COM) of the external terminal block 55 and provides it as a DC power supply signal, and the AC input contact point. When receiving AC power supply between the contact terminal (X1) and the common terminal (COM) of the external terminal block 55, the transmission signal connected to the photocoupler (PT1) is a signal amplifier (50) in which the array of Darlington transistors And amplified by (51), and the amplified signal is sent to input data buffers (24) and (25).

At this time, the program is executed by the EP-ROM 16 containing the main program so that the address A0 is "low" from the central control unit 10 and the input control IORD signal is "high". When it is sent to the terminals (A) and (B), the "low" signal is output from the output terminal (Y2), and the data buffer 24 associated with this signal is selected, and data input therefrom is inputted. Then, it is carried on the data bus toward the output interface 17, and from the control terminal DIR of the bidirectional bus transceiver 22 to the control terminal DIR of the transceiver 22 to the control terminal DIR of the bidirectional bus transceiver 22. Since the "high" signal of the IORD output from the control device 10 is input, the input data loaded on the input and output data buffers 24 and 25 is input to the central control device 10.

On the other hand, if the address A0 is "high" from the central control unit 10 and the input control IORD signal is applied to the address decoder unit 19 as "high", its output terminal Y3 is also "low". "The signal is output and the data buffer 25 associated with this signal is selected, and the data input therefrom is carried on the data bus toward the input and output interface 17, and at the same time, the bidirectional bus transceiver 22 Since the " high " signal of the IORD is input to the terminal DIR, the data loaded in the input / output data buffer 26 is input to the central controller 10.

Subsequently, after the input data of the input data buffers 24 and 25 respectively allocated by the IORD signal of the central controller 10 are read out, the central elimination device 10 reads the EP-ROM 16. It decides whether to output by the program command, and inputs the address signal and IOWR signal of the input processed data, and through the output interface 17, 18, the bidirectional bus transceiver 22 and the address decoder Will be sent to (19).

That is, the bidirectional bus transceiver 22 inputs an IORD " low " signal of the control signal to the signal DIR, and is thus mounted on the data input / output interface 17 of the data bus of the central controller 10 side. It becomes.

At this time, when the address A0 signal is "high" at terminal (A) of the address decoder 19 and the IOWR control signal is "high" at the (C) terminal, the output terminal Y5 is connected to the output terminal Y5. A low signal is output, and when the low signal rises, the gate direction of the bidirectional bus transceiver 22 is switched from input to output, and at the same time, the data signal applied to the output data buffer 23 is output to the output data bus. The signal is delivered to the signal amplifier 52, which is then amplified by the signal amplifier 52 and then sent to the output driver circuits 26-33.

At this time, if the driving point suitable for the input contact signal is set as the relay Ry1 according to the initial specification condition when configuring the programmable logic controller circuit, the coil is excited to the relay Ry1 by the amplified applied signal and its contact Ry1a is excited. If the driving point corresponding to the input contact signal is closed and is set to the photo coupler PT3, the signal amplified from the signal amplifier 52 is insulated by the photocoupler PT3 and is outputted through the output circuit 56. Output to 58.

In addition, as in the above means, the signal amplified from the signal amplifier 52 is applied to the triac driving circuit 57, and at the same time triggers the triac (TRIAC) to output to the output terminal block (58).

On the other hand, the address decoder 19 does not specify only its own input and output contact data, but a plurality of other programmable logic controllers (hereinafter referred to as expansion units) having the same configuration and operation as described above may be sequentially added. At this time, as shown in FIG. 5, the identifier information sent from the central controller 10, that is, the address signals A0-A6 and the control signals IORD and IOWR are received by the input and output interface 18, and then the address is received. Once sent to the decoder 19, it is confirmed that it is its own address, it is recognized as its own address, and the above-described process is performed to transmit and receive the input and output data, and if it is not its own address, The central control unit sends the input and output data buffers 23, 24 and 25 applied to the unit 100 (programmable logic controller of the present invention) to the floating circuit (same as the adder) 20. (One 0) It is added to the delimiter information, it is confirmed that the address of their own from the first extended unit 200 that is provided with the output of the aggregated basic unit 100, this also the address corresponding to the expansion unit 200 Then, the related input / output is executed by itself. Otherwise, the number of input / output ports 23 ', 24', and 25 'used by this unit 200 is sent to the adder 20' and the expanded unit. It is added with the output information of 200 and then output for input of the enlarged unit n.

In the end, the first input, output data buffers (23 "), (24") and (25 ") designated addresses of the expansion unit (n) are used by the basic unit 100 and the number of ports used by the expansion unit 200. In this way, even if a unit having various input / output port numbers is freely connected, the address number is assigned to the central control unit 10 sequentially from the next unit.

As described above, the programmable logic controller of the present invention consists of 16 input points and 8 output points, and can be configured by DC, AC input, relay output, transistor, and triac according to input and output configuration circuits. Not only this, but also by the address decoding method, it is possible to increase the expansion unit regardless of the order or score.

Claims (6)

In the conventional programmable logic controller which exchanges input and output data by the program of the brain part composed of the EP-ROM 16, the RAM 15, and the central controller 10, provided from the central controller 10. The identifier information (address, control, data signal) is selected through the input and output interface 18 and the address decoder 19 to select their own input and output data buffers 23, 24, and 25. The expansion units 200 and (n) may be selected through the compensation circuit (adder) 20 and selector information may be selected. The input / output interface 17 connected to the central control unit 10 may include a bidirectional bus ( 22) input / output data buffers 23, 24, and 25 are connected to the address data control bus, and the control signal input terminals DIR and G of the bidirectional bus transceiver 22 are connected to each other. Even if an IORD signal and an address signal A0 of the central controller 10 are applied. The input and output data buffers 23, 24, and 25 are connected to the signal amplifiers 50, 51, and 52 which are arrayed using a transistor connected by Darlington as a pair. In each of the signal amplifiers 50, 51, and 52, one input driver circuit 34 is composed of eight two pairs, and sixteen input driver circuits 26 are composed of eight two pairs of six input drivers. Programmable, characterized in that the circuit (34-41), (42-49) and one output driver circuit 26 is composed of eight pairs of all eight output driver circuits (26-33) are divided and configured Logic controller. The signal of claim 1, wherein the input driver circuits (34-41) and (42-49) are composed of a light emitting element (LED1) indicating an input state, a photocoupler (PT1), and an RC filter circuit (53). Programmable logic controller, characterized in that it can include a driver circuit (34) for direct current contact signal input to deliver the to the signal amplifier (50) or (51). 2. The input driver circuits (34-41) and (42-49) are rectifiers (54) for rectifying AC power to DC, photocoupler (PT2) RC filters, and light emitting elements (LED2) for indicating an input state. Programmable logic controller, characterized in that it can be configured to rectify the AC contact signal to a direct current, and then to transmit to the signal amplifier (50), 51 as an isolated signal. 2. The output driver circuit (26-33) according to claim 1, wherein the output driver circuits (26-33) consist of a light emitting element (LED3) indicating an output state, a relay (Ry1), and a contact (Ry1a) to be relayed by an amplified signal output from the signal amplifier 52. A programmable logic controller, characterized in that (Ry1) is driven to select to operate the load side connected to the output terminal block (58). 2. The output driver circuit 26-33 of claim 1, wherein the output driver circuits 26-33 include a light emitting element LED4, a photocoupler PT3, a resistor R16, a transistor Q1, and a diode D1-D2 indicating an output state. Programmable logic, characterized in that the amplifier circuit output from the signal amplifier 52 consisting of the output circuit 56 is isolated to the photocoupler (PT3) can be selected to operate the load side connected to the output terminal block (58) controller. The output driver circuit 26-33 includes a light emitting element LED5 indicating an output state, a phototriac PD1, and a triac driving circuit 57. The output driver circuits 26 to 33 output the signal from the signal amplifier 52. And a triac (TRIAC) driving point of the amplified signal, the load side connected to the output terminal block 58 may be selected to operate.