KR910008818A

KR910008818A - Integrated CMOS circuit

Info

Publication number: KR910008818A
Application number: KR1019900016859A
Authority: KR
Inventors: 요세피우스 마리아 베엔드리크 헨드리쿠스; 안토니우스 요한네스 마리아 반 덴 엘샤우트 안트레이스; 빌렘 하르베르트스 디르크
Original assignee: 프레데릭 얀 스미트; 엔. 브이. 필립스 글로아이람펜파브리켄
Priority date: 1989-10-24
Filing date: 1990-10-22
Publication date: 1991-05-31
Also published as: KR0185976B1; ATE147543T1; RU2025829C1; EP0425032A1; JP3060235B2; JPH03152970A; NL8902629A; UA27693C2; DE69029642T2; EP0425032B1; DE69029642D1

Abstract

A gate array circuit comprising a row of consecutively arranged n-channel transistors and an adjacent row of p-channel transistors. Both rows are composed of at least three subrows with two subrows of narrow transistors and one subrow of wide transistors, of which the channel width is at least three times the width of the narrow transistors. The gate electrodes are common to the three subrows. Preferably, the wide subrow is arranged centrally between the narrow subrows. This construction affords the advantage of a very high density and a very high flexibility in designing the functions to be realized.

Description

Integrated CMOS circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제4도는 제1도에서, 각각 라인 II-II, III-III 및 IV-IV에 따라 자른 회로의 단면도.4 is a cross-sectional view of the circuit in FIG. 1 taken along lines II-II, III-III and IV-IV, respectively.

제5도는 배타적 NOR게이트 (EXC, NOR)의 회로 다이어그램 도시도.5 is a circuit diagram illustration of an exclusive NOR gate (EXC, NOR).

Claims

N-channel MOS transistor first row and adjacent parallel second row having a common gate electrode in the form of conductor tracks extending transversely in the direction of the two rows, and conductor tracks extending transversely in the row direction on the two rows in front A gate array type integrated CMOS circuit having a semiconductor body provided with a first row of P-channel transistors having a common gate electrode and a second parallel row adjacent to each other, wherein the n-channel transistors have a first row and a second row. In addition to the P-channel transistors first and second rows, one (at least) each other row of the (at least) of the n-channel transistor and the P-channel transistors is placed (denoted as the third row), which is the first and second rows. Connected in parallel to each other, the gate electrodes of the n-channel transistors first and second rows simultaneously constitute the gate electrodes of the third row of the n-channel transistors, and the first and second gate electrodes of the P-channel transistors. The two low gate electrodes simultaneously constitute the third low gate electrode of the P-channel transistor, while the n-channel transistor and the P-channel transistor each of the third low transistors are the first of each of the n-channel transistor and the P-channel transistor. And a width that is at least three times the width of the transistor in the second row.

2. The field effect and transistor width of the third row of the n-channel transistor and the third row of the P-channel transistor are respectively equal to the first and second rows of the n-channel transistor and the first row of the n-channel transistor and the P-channel transistor. And at least four times the width of each field effect transistor in each of the second rows.

3. The third row of claim 1 or 2, wherein the third rows of the n-channel transistor and the P-channel transistor are each disposed between the n-channel transistor first and second rows and between the P-channel transistors first and second rows. Integrated CMOS circuit, characterized in that.

※ Note: The disclosure is based on the initial application.