KR910008418A - Baud Rate Measurement System - Google Patents

Baud Rate Measurement System Download PDF

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Publication number
KR910008418A
KR910008418A KR1019890015833A KR890015833A KR910008418A KR 910008418 A KR910008418 A KR 910008418A KR 1019890015833 A KR1019890015833 A KR 1019890015833A KR 890015833 A KR890015833 A KR 890015833A KR 910008418 A KR910008418 A KR 910008418A
Authority
KR
South Korea
Prior art keywords
data
pal
measurement system
rate measurement
baud rate
Prior art date
Application number
KR1019890015833A
Other languages
Korean (ko)
Inventor
염근혁
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019890015833A priority Critical patent/KR910008418A/en
Publication of KR910008418A publication Critical patent/KR910008418A/en

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Abstract

내용 없음No content

Description

직렬포트의 보드율 측정시스템Baud Rate Measurement System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 본 발명 직렬포트의 보드율 측정시스템에 대한 블록도,1 is a block diagram of a baud rate measurement system of the serial port of the present invention;

제 2 도의 (가)는 제1도 전송데이타(TXD)의 파형도이고, (나)는 제1도 샘플링클럭발생부(1)의 출력파형도.2A is a waveform diagram of the first-degree transmission data TXD, and (B) is an output waveform diagram of the sampling clock generation unit 1 in FIG.

Claims (1)

사용자의 선택에 따라 각기 다른 샘플링클럭신호를 출력하는 샘플링클럭발생부(1)와, 상기 샘플링클럭발생부(1)로부터 입력되는 클럭신호를 입력함과 아울러 인버터(2)를 통하는 전송데이타(TXD)를 입력하여 일정갯수의 데이타를 샘플링하는 PAL(3)과, 상기 PAL(3)로부터 입력되는 직렬데이타를 병렬데이타로 래치하는 시프트 레지스터(4)와, 상기 시프트레지스터(4)로부터 입력되는 바이너리데이타를 세븐세그먼트(7a,7b) 발광다이오드의 해당코드로 엔코드하여 출력하는 PAL(5a,5b)로 구성된 것을 특징으로 하는 직렬포트의 보드율 측정시스템.According to the user's selection, the sampling clock generator 1 outputs different sampling clock signals, the clock signal input from the sampling clock generator 1, and the transmission data through the inverter 2 (TXD). ) PAL (3) for sampling a certain number of data, the shift register (4) for latching serial data input from the PAL (3) as parallel data, and the binary input from the shift register (4) A serial port baud rate measurement system, comprising: PAL (5a, 5b) for encoding and outputting data to a corresponding code of a seven segment (7a, 7b) light emitting diode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890015833A 1989-10-31 1989-10-31 Baud Rate Measurement System KR910008418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890015833A KR910008418A (en) 1989-10-31 1989-10-31 Baud Rate Measurement System

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890015833A KR910008418A (en) 1989-10-31 1989-10-31 Baud Rate Measurement System

Publications (1)

Publication Number Publication Date
KR910008418A true KR910008418A (en) 1991-05-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890015833A KR910008418A (en) 1989-10-31 1989-10-31 Baud Rate Measurement System

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KR (1) KR910008418A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100327546B1 (en) * 1998-09-18 2002-03-14 서평원 Method And Circuit For Subscription Arbitration Of Bus Master

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100327546B1 (en) * 1998-09-18 2002-03-14 서평원 Method And Circuit For Subscription Arbitration Of Bus Master

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