KR910005925Y1 - Tv mode switching compensation circuit - Google Patents
Tv mode switching compensation circuit Download PDFInfo
- Publication number
- KR910005925Y1 KR910005925Y1 KR2019880009814U KR880009814U KR910005925Y1 KR 910005925 Y1 KR910005925 Y1 KR 910005925Y1 KR 2019880009814 U KR2019880009814 U KR 2019880009814U KR 880009814 U KR880009814 U KR 880009814U KR 910005925 Y1 KR910005925 Y1 KR 910005925Y1
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- KR
- South Korea
- Prior art keywords
- switching
- voltage
- compensation circuit
- mode switching
- clamping
- Prior art date
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/775—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/16—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
- H04N5/18—Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level by means of "clamp" circuit operated by switching circuit
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
Abstract
내용 없음.No content.
Description
첨부도면은 본 고안의 실시회로도.The accompanying drawings are embodiments of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
2 : 클램핑부 3 : 스위칭부2: clamping part 3: switching part
D1: 다이오드 ZD1,ZD2: 제너다이오드D 1 : diodes ZD 1, ZD 2 : zener diodes
R1-R6: 저항 Q1,Q2: 트랜지스터R 1 -R 6 : Resistor Q 1, Q 2 : Transistor
본 고안은 텔레비젼, 특히 21핀 유로스카트잭(EURO SCART JACK)을 채용하는 오디오/비디오(이하 A/V라 함)기능의 텔레비젼에 있어서, A/V 모우드 절환시 불확실한 스위칭전압 레벨에 의한 스위칭 오동작을 방지하도록 된 모우드스우칭 보상회로에 관한 것이다.The present invention is a switching malfunction due to an uncertain switching voltage level during A / V mode switching in a television, especially an audio / video (hereinafter referred to as A / V) function employing a 21-pin EURO SCART JACK. The present invention relates to a mode punching compensation circuit.
21핀 유로스카트잭은 외부비디오신호입력잭을 구비하여, 티브이신호와 외부비디오신호 모우드를 절환하는 기능을 갖는 집적회로로서, 특히 유럽지역수출모델에 많이 채용되고 있다.The 21-pin Euroscat jack has an external video signal input jack, and has an integrated circuit having a function of switching between a TV signal and an external video signal mode, and is particularly employed in European export models.
그러나 이와같은 21핀 유로스카트잭을 채용하는 텔레비젼에 있어서, A/V절환시 이 21핀 유로스카트 잭에 입력되는 스위칭 전압이 '로우'레벨인 경우 0-3V, 그리고 '하이'레벨인 경우 9-12V만으로 규정되어 있기 때문에 이들의 중간전압인 3-8.9V의 전압이 입력될 경우 종종 스위칭 오동작이 발생하여 정상적인 모우드절환 기능이 이루어지지 않는 폐단이 있었다.However, in a TV employing such a 21-pin Euroscat jack, when the A / V switching, the switching voltage input to this 21-pin Euroscat jack is 'low' level 0-3V, and 'high' level 9 Since it is specified as -12V only, when the intermediate voltage of 3-8.9V is inputted, switching malfunction often occurs, and there is a closed stage in which the normal mode switching function is not performed.
본 고안의 목적은 이와같은 폐단을 해결하기 위한 것으로, 21핀 유로스카트잭으로 입력되는 A/V구동용 스위칭전압을 제너다이오드의 임계전압을 이용하여 클램핑시키고, 이 클램핑출력전압에 의해 TV/ 비디오 스위칭출력전압을 선택함으로서 선택모우드에 따라 정확한 스위칭전압레벨이 유지되도록 안출한 것으로서, 이하 본 고안의 구성 및 작용효과를 첨부도면에 의해 상세히 설명한다.The purpose of the present invention is to solve this problem, and clamps the switching voltage for A / V driving input to the 21-pin Euro-Scatter jack by using the zener diode threshold voltage, and by this clamping output voltage By selecting the switching output voltage to maintain the correct switching voltage level according to the selection mode, the configuration and operation effects of the present invention will be described in detail by the accompanying drawings.
본 고안의 회로는 통상의 21핀 유로스카트잭(1)에 입력되는 A/V구동용 스위칭전압을 일정전압레벨로 클램핑시키는 클램핑부(2)와 이 클램핑부(2)의 출력전압에 의해 스위칭제어되어 TV/비디오 스위칭전압을 출력하는 스위칭부(3)로 구성된다.The circuit of the present invention is switched by a clamping part (2) for clamping the switching voltage for A / V driving input to the conventional 21-pin Euro-ska jack (1) to a constant voltage level and the output voltage of the clamping part (2). And a switching section 3 which is controlled to output the TV / video switching voltage.
본 고안의 실시예에 있어서, 클램핑부(2)가 역전류방지용 다이오드(D1), 임피이던스매칭용 저항(R1) 및 제너다이오드(ZD1)(ZD2)로 구성되고, 스위칭부(3)가 상호역동작하도록 된 트랜지스터(Q1)(Q2) 및 저항(R2-R6)으로 구성된다.In the embodiment of the present invention, the clamping portion 2 is composed of a reverse current prevention diode (D 1 ), impedance matching resistor (R 1 ) and Zener diode (ZD 1 ) (ZD 2 ), the switching unit 3 ) Are composed of transistors Q 1 (Q 2 ) and resistors R 2 -R 6 , which are interoperable.
미설명 부호중 a는 21핀 유로스카트잭(1)의 A/V 스위칭전압입력단자, B+는 직류전원단자, 4는 TV/비디오 스위칭전압출력단자이다.In the description, a denotes an A / V switching voltage input terminal of the 21-pin Euroscat jack 1, B + is a DC power supply terminal, and 4 is a TV / video switching voltage output terminal.
이와같이 구성되는 본 고안에 있어서, 21핀 유로스카트잭(1)의 단자(a)로 입력되는 A/V 구동용 스위칭전압 레벨이 0-8.9V 범위로 입력될 경우 클램핑부(2) 내의 직렬연결된 제너다이오드(ZD1)(ZD2)가 '오프'상태에 있도록 그 임계전압(제너전압)이 설정되는데, 이 제너다이오드(ZD1)와 단자(a)사이에 연결된 다이오드(D1)는 역전류방지용이며, 저항(R1)은 21핀 유로스카트잭(1)에 대한 회로의 내부임피이던스용 저항이다.In the present invention configured as described above, when the switching voltage level for A / V driving input to the terminal a of the 21-pin euro ska jack 1 is input in the range of 0-8.9V, The threshold voltage (Zener voltage) is set so that the Zener diode ZD 1 (ZD 2 ) is in the 'off' state, and the diode D 1 connected between the Zener diode ZD 1 and the terminal a is reversed. It is for preventing the current, and the resistor R 1 is a resistance for the internal impedance of the circuit for the 21-pin euroscat jack 1.
따라서, 단자(a)로 입력되는 스위칭전압이 0-8.9V일 경우 이 전압을 클램핑부(2)를 통과하지 못하게 되므로 스위칭부(3)내의 트랜지스터(Q1)가 '오프'되고, 이에의해 트랜지스터(Q2)가 저항(R4)(R5)을 통한 베이스전압공급에 의해 '턴온'됨으로써 TV/비디오스위칭전압 출력단자(4)의 전압레벨은 '로우'레벨상태로 유지된다.Therefore, when the switching voltage input to the terminal a is 0-8.9V, the voltage cannot pass through the clamping part 2, so that the transistor Q 1 in the switching part 3 is 'off', thereby The transistor Q 2 is 'turned on' by the base voltage supply through the resistors R 4 and R 5 so that the voltage level of the TV / video switching voltage output terminal 4 remains at the 'low' level.
한편, 단자(a)로 입력되는 A/V 구동용 스위칭전압이 9V 이상일 경우, 클램핑부(2)내의 제너다이오드(ZD1)(ZD2)가 '온'되는데, 이에 의해 상기의 A/V 구동용 스위칭전압이 이들 제너다이오드(ZD1)(ZD2)를 통한 후 스위칭부(3) 내의 저항(R2)(R3)에 의해 분압된 상태에서 트랜지스터(Q1)의 베이스에 인가된다. 따라서 이 트랜지스터(Q1)가 '턴온'되고, 이에 따라 트랜지스터(Q2)는 그 베이스가 '로우'레벨상태로 되어 '턴오프'됨으로서 TV/비디오 스위칭전압 출력단자(4)는 저항(R6)을 통해 B+전압이 인가되어 '하이'레벨로 된다.On the other hand, when the A / V driving switching voltage input to the terminal a is 9 V or more, the zener diodes ZD 1 and ZD 2 in the clamping unit 2 are 'on', whereby the A / V The driving switching voltage is applied to the base of the transistor Q 1 in a state in which it is divided by the resistors R 2 and R 3 in the switching unit 3 after passing through these zener diodes ZD 1 and ZD 2 . . Therefore, the transistor Q 1 is 'turned on', and thus the transistor Q 2 is 'turned off' with its base at the 'low' level state, so that the TV / video switching voltage output terminal 4 becomes the resistor R. 6 ), the voltage B + is applied to the 'high' level.
여기서, 저항(R4)(R6)는 각 트랜지스터(Q1)(Q2)의 스위칭동작을 하기 위한 풀업저항이다.Here, the resistors R 4 and R 6 are pull-up resistors for switching the transistors Q 1 and Q 2 .
이상과 같이 본 고안은 21핀 유로스카트잭을 사용하는 A/V기능의 텔레비젼에 있어서, A/V모우드절환시 '하이' 또는 '로우'의 스위칭전압레벨을 정확히 유지시켜줌으로서 스위칭 오동작을 방지할 수 있는 유용한 고안이다.As described above, the present invention prevents switching malfunction by maintaining the high or low switching voltage level during A / V mode switching in an A / V function television using a 21-pin Euroscat jack. It is a useful design.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880009814U KR910005925Y1 (en) | 1988-06-24 | 1988-06-24 | Tv mode switching compensation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019880009814U KR910005925Y1 (en) | 1988-06-24 | 1988-06-24 | Tv mode switching compensation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR900001989U KR900001989U (en) | 1990-01-19 |
| KR910005925Y1 true KR910005925Y1 (en) | 1991-08-12 |
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ID=19276656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019880009814U KR910005925Y1 (en) | 1988-06-24 | 1988-06-24 | Tv mode switching compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR910005925Y1 (en) |
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1988
- 1988-06-24 KR KR2019880009814U patent/KR910005925Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR900001989U (en) | 1990-01-19 |
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