KR910005488B1 - Apparatus for converting a-law to u-law in pcm multiflexing system - Google Patents

Abstract

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Description

Inverter between A / μ laws

1 is a block diagram schematically showing the configuration of the present invention.

2 is a detailed configuration diagram of a conversion circuit.

3 illustrates one embodiment of a conversion circuit.

4 is a TDM bus structure diagram.

5 is a detailed configuration diagram of the timing generation circuit.

6 is a detailed configuration diagram of the conversion control circuit.

* Explanation of symbols for main parts of the drawings

10: conversion circuit 20: timing generating circuit

30: conversion control circuit 40: time switch

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a PCM compression law converting apparatus, and more particularly, to an apparatus for converting between A / μ laws, which converts between a?

Conversion between heterogeneous transmission methods is essential in digital inter-contact between WL stations that use heterogeneous transmission methods and heterogeneous transmission methods. Channel reconfiguration and line signals are necessary to enable mutual transmission between both transmission methods. There is a need for a converting apparatus for performing the method conversion and the PCM compression law conversion. The present invention relates to a converter that performs a PCM compression law conversion function among such converters.

The transmission methods widely used in the world are North American (NAS) and European (CEPT). The North American system consists of 24 channels of one frame, and all 24 channels are allocated as voice channels. Bit 8 of the first channel of the first frame is used as the signal channel and μ law is used for the companding law of the PCM channel.In the European method, 32 frames are used as one frame consists of 32 channels, and the rest is used as the voice channel. Two channels are used as signal and frame synchronization channels, and the A law is used as the companding law of the PCM channel.

The existing transmission method in Korea adopts the North American method, which is a European method that can meet this demand because it lacks the full channel transmission capacity of 64 Kb / s required for future inter-ISDN transmission. In order to convert the existing transmission method, however, a lot of expenses and time are required to modify the existing transmission method, so the newly introduced European method and the existing North American method are mixed to enable the interconnection between the two methods. It is suitable for and economical.

In addition, there is a need for a conversion device that enables interconnection with a domestic North American method even when intercommunicating with countries applying the European method.

An object of the present invention is to transfer the transfer method in a dual transfer type conversion apparatus that is located on the transmission path between the two methods in a mixed transmission environment of the North American and European methods or between countries. A typical function of the device is to provide an A / μ law converter that performs the A / μ law conversion function.

It is still another object of the present invention to provide an A / μ law-to-law conversion device that can be implemented more economically and stably to perform a conversion function and to secure flexibility in network application.

Therefore, the present invention is a means for achieving the above object, the timing generating means for generating the necessary timing, the timing signal of the timing generating means and the contents of the transmission data from the time switch in the central control unit (CCU) of the heterogeneous signal converting apparatus. Conversion control means for generating a control signal prohibiting the conversion function between A / μ laws if the transmission data is not a voice PCM channel and is a digital data channel, and is connected to a time switch and transmission interface in the CCU via a TDM bus and Input / output data, input the timing signal of the timing generating means and the control signal of the conversion control means to perform the conversion function between the A / μ law of the voice PCM channel among the data transmitted through the TDM bus and convert the converted voice PCM Provided is an A / μ law-to-law conversion device composed of conversion means for sending a channel through a TDM bus.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

는 프레임 동기신호를,

는 프레임 동기 패턴 검출을 위한 클럭펄스를 각각 나타낸다.1 is a block diagram showing the configuration of the present invention. In the figure, 10 denotes a conversion circuit, 20 denotes a timing generating circuit, 30 denotes a conversion control circuit, 40 denotes a time switch, and ST ₀ -1 to ST _0-2 denote SST buses of the time switch.

Frame synchronization signal,

Denote clock clocks for frame synchronization pattern detection, respectively.

The conversion circuit 10 is a direct pressure law converting function, i.e., A / Performs the law conversion function or μ / A law conversion function to transmit the voice PCM channel converted to the TDM bus again.

The timing generation circuit 20 generates a timing necessary for the conversion circuit 10 and transmits the timing to the conversion circuit 10.

The conversion control circuit 30 generates the A / μ law conversion signal or the A / μ law conversion inhibit signal under the control of the time switch 40 to directly control the conversion circuit in units of channels.

2 is a detailed configuration diagram of the conversion circuit 10, and FIG. 3 is an exemplary view of the conversion circuit.

는 음성 PCM채널에 동기된 클럭펄스를, LC１ 및 PL１은 타이밍 발생회로(20)의 타이밍 신호를, AUC는 변환 제어회로(30)의 제어신호를 각각 나타낸다.In the figure, 11 is a serial / parallel conversion circuit, 12 is a PROM memory, 13 is a parallel / serial conversion circuit, C2 and

Denotes a clock pulse synchronized with the voice PCM channel, LC1 and PL1 denote timing signals of the timing generation circuit 20, and AUC denotes control signals of the conversion control circuit 30, respectively.

The PCM serial data on the TDM bus is converted into parallel channel data in units of 8 bits by the serial / parallel conversion circuit 11 driven by the timing signal (C2, LC1 in FIG. 3) of the timing generation circuit 20.

The parallel channel data is utilized for the address designation of the PROM memory 12 in which the A / μ law conversion table is stored, and is input to the address input terminals A0-A7 of the PROM memory 12, and the conversion control circuit The control signal AUC of 30 is input to the address input terminal A8.

At this time, the control signal AUC performs an A / μ law conversion function by setting '0' for the voice PCM channel and '1' for the data channel so that the A / μ law conversion is prohibited.

The contents of the designated address of the PROM memory 12 are conversion code values corresponding to the input audio PCM channel data, and are output in parallel (8 bits) through the output terminal Q1-Ｑ８, and the parallel / serial conversion circuit 13 ) Is converted back to serial data and sent over the TDM bus.

The A / μ law conversion table built in the PROM memory 12 is shown in the following table. In the following table, Table 1 shows the case where the PCM channel data on the input TDM bus is μ law, and Table 2 shows the case where the PCM channel data on the input TDM bus is A law.

TABLE 1

TABLE 2

Since the PROM memory 12 has a 512-byte capacity and each address is 8 bits (Table 1), the μ law data is used for addressing purposes, and the 8 bit data of the A law corresponding to the μ law is assigned to the address. Stored.

The converted PCM data is stored in 0 to 255 addresses of the 512 byte memory area, and the same data as the input PCM data is stored and used in 256 to 511 addresses.

In the preferred embodiment, the serial / parallel conversion circuit 11 used 74HC 595 chip, PROM memory 2 used 82S147 chip, and the parallel / serial conversion circuit 13 used 74HC165 chip.

When the chips are used, the total delay time until the input PCM channel data is converted to the output PCM channel data and outputted is only 4 µS, which is a one channel data transmission time, thereby minimizing the transmission delay.

4 is a TDM bus structure diagram.

The European method is shown here.

와 채널(CH)의 각 비트에 동기된 클럭펄스(C２)와 프레임 동기검출을 위한 상기 클럭펄스(C２)의 반주기를 갖는 클럭펄스(C４）를 포함하고, 각 바이트(8비트)단위의 채널에는 음성 PCM데이터와 디지털 데이터 정보를 포함하고 있다.Frame is composed of 32 channels (CH) and 1 channel (CH) is composed of 8 bits.

And a clock pulse C4 synchronized with each bit of the channel CH, and a clock pulse C4 having a half period of the clock pulse C2 for frame synchronous detection, and each byte (8-bit) channel. Contains voice PCM data and digital data information.

5 is a detailed configuration diagram of the timing generation circuit 20. As shown in FIG.

와 클럭펄스

를 D플립플롭(21,22)과 인버터(23), AＮＤ논리회로(24)로 조합하여 다단 바이너리 카운터(25)의 입력단(A)으로 연결하고, 상기 다단 바이너리 카운터(25)는 상기 조합된 입력과 클럭펄스

를 입력하여 여러개로 분주시킨 클럭펄스를 출력단자(QＡ－ＱＩ)를 통해 출력하여 PROＭ(26)의 어드레스 번지를 지정하여, 상기 PROＭ(26)은 해당 어드레스의 내용을 병렬로 출력하고, 타이밍 발생기(27)는 상기 병렬출력을 입력단자(A－Ｈ)를 통해 입력하여 각 필요회로에 필요한 타이밍 신호를 출력단자(1Q－８Ｑ)를 통해 출력한다. 상기 타이밍 발생기(27)의 1Q의 출력(PL1)은 병렬/직렬 변환회로(제3도의 13)에, 2Q의 출력(LC１）은 직렬/병렬 변환회로(제3도의 11)에 ５Ｑ의 출력(LC2)는 변환제어회로(30)에 연결되어 필요한 타이밍을 제공한다.Frame sync signal

And clock pulse

Is coupled to the input terminal A of the multi-stage binary counter 25 by combining the D flip-flops 21 and 22, the inverter 23, and the ADN logic circuit 24, and the multi-stage binary counter 25 is Input and Clock Pulses

Inputs a plurality of divided clock pulses through an output terminal (QA-XI), specifies an address address of the PROM 26, and the PROM 26 outputs the contents of the corresponding addresses in parallel, and generates a timing generator. (27) inputs the parallel output through the input terminal A-H, and outputs a timing signal necessary for each necessary circuit through the output terminal 1Q-Q. The output PL1 of 1Q of the timing generator 27 is a parallel / serial conversion circuit (13 in FIG. 3), and the output LC1 of 2Q is an output of 5 kW to the serial / parallel conversion circuit (11 in FIG. 3). LC2) is coupled to the conversion control circuit 30 to provide the necessary timing.

In the preferred embodiment, the D flip-flops 21 and 22 use 74LS74 chips, the multi-stage binary counter 25 uses 74HC4040 chips, the PROM 26 uses 82S147, and the timing generator 27 uses 74L574.

6 is a detailed configuration diagram of the conversion control circuit 30.

The conversion control circuit 30 is a time switch 40 capable of switching the channel data on the TDM bus from the CCU of the heterogeneous signal converting apparatus that knows in advance whether the channel data on the TDM bus is the PCM channel or the digital data channel. ) And generates a timing for controlling the execution or prohibition of the conversion circuit 10 in units of channels by encoding the received information.

The two decoders 31 and 32 are provided with the information signals ST0-1 and ST0-2 from the time switch 40, the clock pulse C2 synchronized with the channel bit pulse, and the 5Q output of the timing generation circuit 20. (LC2) is inputted and output as an 8-bit parallel signal to designate the address of the buffer register 33. The buffer register 33 converts the control circuit AUC of the conversion circuit 10 to the first output terminal Q1. The output signal is connected to the input terminal A8 of PROM (12 in FIG. 3) of the conversion circuit 10. If the channel data on the TDM bus is the voice PCM channel, the control signal AUC becomes 0 to perform the conversion function. In the digital data channel, the control signal AUC becomes '1' to disable the conversion function.

In the preferred embodiment, the decoders 31 and 32 used 74H5 595 chips and the register buffer 33 used 74HC541 chips.

The A / μ law conversion device configured and operated as described above has the following effects.

First, a very simple conversion circuit can be constructed by storing and using the calculated code conversion values for 128 levels except positive and negative codes in PROM memory so as to have the minimum PCM conversion distortion when converting between A / μ laws.

Second, transparency of information transmission can be realized by providing the ability to prohibit conversion between A / μ laws for each channel to enable high-speed data transfer of 56 ms / s or 64 ms / s.

Third, by performing the real-time conversion function directly on the TDM bus, the transmission delay is reduced to about 4 μS to minimize delay.

Fourth, a more economical A / μ law conversion function can be realized, and the stock of transmission quality and flexibility in network application can be realized.

Claims (4)

A device for converting between A / μ laws of a North American transmission system and a European transmission heterogeneous signal conversion apparatus including a channel reconstruction device, a signal conversion device, an A / μ law conversion device, and a central control device, Frame Sync Clock

And clock pulse

The timing generating means 20 for outputting timing signals through the frequency divider circuit, the timing signal of the timing generating means 20 and the contents of the transmission data from the time switch 40 in the central control apparatus (STO1, ST02). Conversion control means 30 for outputting a control signal (AUC) for inputting the transmission data to a voice PCM channel and performing an A / μ law conversion function, and for prohibiting conversion between A / μ laws if the digital data channel; Connected to the time switch 40 and the transmission interface and the TDM bus in the central control unit to input and output serial data, and the timing signals LC1 and PL1 of the timing generating means 20 and the conversion control means 30. A conversion means (10) which inputs a control signal (AUC) to perform the A / μ law conversion function of the voice PCM channel among the data transmitted through the TDM bus and transmits the converted voice PCM channel through the TDM bus. Converter between A / μ law, characterized in that a generated. 2. The converting means (10) according to claim 1, wherein the converting means (10) connects the serial / parallel converting circuit (11), the PROM memory means (12), and the parallel / serial converting circuit (13) in succession and inputs them through a TDM bus in any direction. A serial data is converted into parallel data and inputted to the PROM memory means 12, and the parallel output converted between A / μ laws of the PROM memory means 12 is converted into serial data and transmitted to the TDM bus. An A / μ law inter converter. 2. A converting means (10) according to claim 1, characterized in that said converting means (10) includes a PRO M memory means (12) for storing A / μ law conversion tables and outputting only converted data corresponding to each input address. / μ-to-law converter. 2. The timing generating means (30) according to claim 1, wherein the timing generating means (30) includes a first D flip flop (21), a second D flip flop (22), an AND gate (24), a multi-stage binary counter (25), a PRO memory device (27), and the like. A timing generator 27 is provided, and a frame synchronization clock is provided at the D terminal of the first D flip-flop.

Input and clock pulse to clock terminal (CＫ).

To input the inverted output Q of the first D flip-flop to the D terminal of the second D flip-flop, and to input the inverted clock pulse C4 to the clock terminal C ', and to input the first and second D flip-flops. A / μ law characterized in that the output of the flop (Q, Q) is connected to the AND gate, the output of the AND gate is connected to the multi-stage binary counter, and subsequently connected to the PROM memory element and the timing generator in series. Inter inverter.

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