KR910005344Y1 - Picture distortion compensating circuit - Google Patents

Picture distortion compensating circuit Download PDF

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Publication number
KR910005344Y1
KR910005344Y1 KR2019860017014U KR860017014U KR910005344Y1 KR 910005344 Y1 KR910005344 Y1 KR 910005344Y1 KR 2019860017014 U KR2019860017014 U KR 2019860017014U KR 860017014 U KR860017014 U KR 860017014U KR 910005344 Y1 KR910005344 Y1 KR 910005344Y1
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South Korea
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current
transformer
horizontal
screen
deflection yoke
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KR2019860017014U
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Korean (ko)
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KR880010964U (en
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송영배
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삼성전자 주식회사
한형수
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/16—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by deflecting electron beam in cathode-ray tube, e.g. scanning corrections
    • H04N3/22—Circuits for controlling dimensions, shape or centering of picture on screen
    • H04N3/23—Distortion correction, e.g. for pincushion distortion correction, S-correction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00—Adaptations of transformers or inductances for specific applications or functions
    • H01F38/42—Flyback transformers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Details Of Television Scanning (AREA)

Abstract

내용 없음.No content.

Description

화면 찌그러짐 보정회로Screen distortion correction circuit

제 1 도는 본 고안의 실시예를 보인 블록도.1 is a block diagram showing an embodiment of the present invention.

제 2 도는 본 고안의 실시예를 보인 상세한 회로도.2 is a detailed circuit diagram showing an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

T1: 플라이백 트랜스 T2: 핀쿠션 트랜스T 1 : Flyback Trans T 2 : Pincushion Trans

TR1: 수평출력 트랜지스터 가 : 파라보라 전류증폭부TR 1 : Horizontal output transistor A: Parabolic current amplifier

나 : 핀 절환부 다 : 전류 증폭부B: pin changer c: current amplifier

본 고안은 텔레비젼 수상기의 화면이 편향 찌그러짐(deflection distortion)현상으로 인하여 실감이 모양이 되는 현상을 방지하며, 화면의 밝기를 일정하게 유지할 수 있는 화면 찌그러짐 보정회로에 관한 것이다.The present invention relates to a screen distortion correction circuit that prevents the appearance of a sense of reality due to deflection distortion of the screen of a television receiver and maintains the brightness of the screen constantly.

텔레비젼 수상관의 형관면은 전자 비임의 편향점을 중심으로 한 구면이 아니므로 주변으로 갈수록 편향점으로 부터의 거리가 멀어진다.The shape of the surface of the television receiver is not a sphere centered on the deflection point of the electron beam, so the distance from the deflection point becomes farther away.

이 때문에 전자 비임을 편향일 경우 가장 먼 거리에 있는 네 구석부분이 편향이 커저서 라스터는 실감이 모양의 찌그러짐을 발생한다.Because of this, when the electron beam is deflected, the four corners at the farthest distance become larger and the raster generates a realistic distortion.

이러한 실감이 모양의 화면을 보정하려면 수평편향전류의 진폭을 수직주사주기로 파라보라(parabora) 형으로 진폭변조해 주면 된다.In order to correct this realistic screen, the amplitude of the horizontal deflection current is modulated into a parabora type with a vertical scanning period.

이와같은 보정파형을 만들기 위하여, 종래에는 저항, 콘덴서 및 가포화 리액터(Pincushion Trans)로 구성된 회로를 사용하여 수평출력쪽의 인덕턴스는 수직보정전류를 많게 하면 작아지고 적게하면 커진다.In order to make such a correction waveform, conventionally, a circuit composed of a resistor, a condenser, and a saturation reactor (Pincushion Trans) is used, and the inductance on the horizontal output side becomes smaller when the vertical correction current increases, and increases when the number decreases.

따라서 수평직쪽의 인덕턴스에 저항과 콘덴서로 구성된 적분회로를 통과하여 만든 파라보라형 전류를 흘려 실감이 모양의 찌그러짐을 보정하였다.Therefore, the parabolic current made by passing through the integrating circuit composed of resistors and condensers was applied to the horizontal inductance to compensate for the distortion of the shape.

그러나 이러한 보정수단은 별도의 수평주파수에 따라 기준치를 정해야하는 번거로움이 따르고, 휴대용 텔레비젼수상기를 시청하고 있는 경우 지역 사정에 따라 수평, 수직동기를 조정하여야 하는 불편함이 있다.However, such a correction means has the inconvenience of having to set a reference value according to a separate horizontal frequency, and if you are watching a portable television receiver has the inconvenience of adjusting the horizontal and vertical synchronization according to the local circumstances.

그러므로 본 고안의 목적은 수평주파수가 15.75kHz, 24kHz, 31.5kHz로 변환되어도 화면의 찌그러짐을 보정할 수 있으며, 화면의 밝기를 일정하게 고품질의 화면을 유지할 수 있는 화면 찌그러짐 보정회로를 제공하는 데 있다.Therefore, an object of the present invention is to provide a screen distortion correction circuit that can correct screen distortion even when the horizontal frequency is converted to 15.75 kHz, 24 kHz, and 31.5 kHz and maintain a high quality screen with a constant brightness of the screen. .

이와같은 목적을 가지는 본 고안은 핀쿠션 트랜스와 수직편향요크 사이에 파라보라 전류증폭부를 구성하고 절환신호에 따라 동작하는 핀절환부로 실감이 모양의 찌그러짐을 보정하고, 플라이백 트랜스와 핀쿠션 트랜스 사이에 전류 증폭부를 연결하여 화면의 밝기를 조정할 수 있게 한 것을 특징으로 한다.The present invention having the above object constitutes a parabolic current amplifier between the pincushion transformer and the vertical deflection yoke, and is a pin switching part operating according to a switching signal to compensate for the distortion of the shape, and the current between the flyback transformer and the pincushion transformer. The brightness of the screen can be adjusted by connecting the amplifier.

이하, 본 고안의 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

제 2 도는 본 고안의 실시예를 보인 상세회로도로, 이에 도시된 바와같이 수평출력 트랜지스터(TR1)의 출력이 플라이백 트랜스(T1)의 1차측에 인가되게 연결되고 상기 플라이백 트랜스(T1)의 2차측은 수상관의 애노우드단자에 연결되며, 화면의 찌그러짐을 보정하기 위하여 수평편향요크(HDY), S보정 콘덴서(C6), 리니어리티 코일(L3), 가포화 리액터 및 수직편향요크(VDY)로 구성된 화면 찌그러짐 보정회로에 있어서, 상기 수직편향요크(VDY)전류가 저항(R1, R2, R3, R4)과 콘덴서(C2)로 바이어스되는 트랜지스터(TR5)의 베이스에 인가되는 연결되고, 이룬 트랜지스터(TR4)에서 증폭하여 핀쿠션 트랜스(T2)의 1차 리액터(L1)에 공급하는 파라보라 전류증폭부(가)와, 에미터가 접지되고 베이스에 모드절환신호가 인가되는 트랜지스터(TR6)의 컬렉터가 저항(R5)를 통하여 상기 파라보라 전류증폭부(가)에 있는 트랜지스터(TR4)의 에미터에 연결되어 모드절환신호에 따라 동작하는 핀 절환부(나)와, 상기 플라이백트랜스(T1)의 이차측의 ABL단자에 인가되는 전류가 저항(R7)(R8)(R9) 및 트랜지스터(TR3)를 바이어스된 회로에 인가되게 연결되어 이를 트랜지스터( TR2)에서 증폭하여 1차 리액터(L1)에 인가하는 전류증폭부(다)로 구성된다.2 is a detailed circuit diagram showing an embodiment of the present invention, and as shown therein, the output of the horizontal output transistor TR 1 is connected to be applied to the primary side of the flyback transformer T 1 and the flyback transformer T The secondary side of 1 ) is connected to the anode terminal of the water pipe, and the horizontal deflection yoke (HDY), the S correction capacitor (C 6 ), the linearity coil (L 3 ), the saturable reactor and the vertical to correct the screen distortion. In the screen distortion correction circuit composed of a deflection yoke (VDY), the transistor (TR 5 ) in which the vertical deflection yoke (VDY) current is biased by the resistors (R 1 , R 2 , R 3 , R 4 ) and the capacitor (C 2 ) The parabolic current amplifying part (a) and the emitter which are connected to the base of the circuit board and amplified by the transistor TR 4 and supplied to the primary reactor L 1 of the pincushion transformer T 2 , applied to the mode switching signal to the base-collector of the transistor (TR 6) that is (R 5) See the para via a current amplifier (A) connected to the emitter of the transistor (TR 4) in the mode with the pin switching (b) operating in accordance with the switching signal, the flyback transformer (T 1 The current applied to the ABL terminal of the secondary side of the circuit is connected to apply the resistors R 7 (R 8 ) (R 9 ) and the transistor TR 3 to the biased circuit, thereby amplifying them in the transistor TR 2 . It consists of a current amplifier (C) applied to the differential reactor (L 1 ).

미설명부호 C1, C3는 결합콘덴서이고, C4, C5는 공진용 콘덴서이며 D1은 댐퍼 다이오드이고, R10은 회로 보호용 저항이며, R11, R12, R13은 전압 강하용 저항이다.Unmarked C 1 and C 3 are coupling capacitors, C 4 and C 5 are resonant capacitors, D 1 is a damper diode, R 10 is a circuit protection resistor, and R 11 , R 12 and R 13 are for voltage drop. Resistance.

이와같이 구성된 본 고안에 따른 화면 찌그러짐 보정회로의 동작을 설명한다.The operation of the screen distortion correction circuit according to the present invention configured as described above will be described.

수직편향요크(VDY)의 전류가 결합 콘덴서(C1)를 통하여 수직주사주기로 파라보라형으로 진폭변조되고, 진폭변조된 신호는 트랜지스터( TR5)(TR4)를 통하여 증폭되어 핀쿠션 트랜스 1차 인덕터(L1)에 파라보라형으로 인가된다. 이때 수평 주파수가 15.75KHz 또는 31.5KHz일 경우에 각각 트랜지스터(TR6)의 베이스에 인가되는 모드절환신호에 따라 트랜지스터(TR4)의 증폭도를 변화시켜서 수평출력을 보정하여 화면 찌그러짐을 보정한다.The current of the vertical deflection yoke (VDY) is amplitude-modulated to parabolic with vertical scanning period through the coupling capacitor (C 1 ), and the amplitude-modulated signal is amplified through the transistor (TR 5 ) (TR 4 ) to pincushion transformer primary. A parabolic type is applied to the inductor L 1 . At this time, when the horizontal frequency is 15.75KHz or 31.5KHz, the distortion of the transistor TR 4 is changed according to the mode switching signal applied to the base of the transistor TR 6 to correct the horizontal distortion to correct the screen distortion.

또한 화면의 밝기가 급변하는 화상에서의 화면 찌그러짐 보정을 살펴보면, 밝은부분에서는 브라운관의 애노우드 전류가 증가하므로 플라이백 트랜스(T1)의 ABL 전압(진공관의 애노우드 전류에 대응한 전압)이 상승하게된다. 따라서 저항(R11)(R13) 에 의한 전압 강하가 크게되며, 이를 결합콘덴서(C3)를 통하여 트랜지스터(TR3)의 베이스에 인가하면 저항(R11)(R13)에의한 전압 상승분에 의하여 저하된 바이어스가 걸리므로 트랜지스터(TR2)의 콜렉터 전류가 작게되어 2차 인덕터(L1) 의 전류가 작아지게되므로 역시 화면 보정을 하게된다.Also, in the image distortion correction in an image in which the brightness of the screen changes rapidly, in the bright part, the anode current of the CRT increases, so that the ABL voltage of the flyback transformer (T 1 ) (voltage corresponding to the anode current of the vacuum tube) increases. Will be done. Therefore, the voltage drop caused by the resistors R 11 and R 13 is increased, and when the voltage drop is applied to the base of the transistor TR 3 through the coupling capacitor C 3 , the voltage increase by the resistors R 11 and R 13 is increased. Since the bias is lowered, the collector current of the transistor TR 2 is reduced, so that the current of the secondary inductor L 1 is reduced, thereby performing screen correction.

이와같이 본 고안은 수평주파수가 변환되어도 화면의 찌그러짐을 보정할 수있으며, 화면의 밝기를 일정하게 고품질의 화면을 유지할 수 있다.As such, the present invention can correct distortion of the screen even when the horizontal frequency is converted, and maintain the screen of high quality with constant brightness of the screen.

Claims (1)

수평출력 트랜지스터(TR1)의 출력을 플라이백 트랜스(T1)에 연결하여 이를 애노우드에 연결시키고 수평 편향요크( HDY), S보정 콘덴서(C6),리니어리티 코일(L3), 가포화 리액터 및 수직편향요크(VDY)로 구성되는 화면 찌그러짐 보정회로에 있어서, 상기 수직 편향요크(VDY)의 전류를 파라보라 전류로 바꾸고 이를 증폭하여 핀쿠션 트랜스(T2)의 1차 리액터(L1) 에 전달하는 파라보라 전류 증폭부(가)와, 수평주파수에 따라 다르게 입력되는 모드절환신호에 따라 증폭도를 변화시켜 핀쿠션 트랜스(T2)의 1차 리액터(L1)에 전달하는 핀 절환부(나)와, 상기 플라이백 트랜스(T1) 의 이차측의 ABL단자에서 인가되는 전류를 증폭하여 핀쿠션 트랜스(T2) 의 1차 리액터(L1)에 인가하는 전류 증폭부(다)로 구성되는 것을 특징으로 하는 화면 찌그러짐 보정회로.Connect the output of the horizontal output transistor (TR 1 ) to the flyback transformer (T 1 ) and connect it to the anode, horizontal deflection yoke (HDY), S compensation capacitor (C 6 ), linearity coil (L 3 ), saturation In the screen distortion correction circuit composed of a reactor and a vertical deflection yoke (VDY), the current of the vertical deflection yoke (VDY) is changed to a parabolic current and amplified to amplify the primary reactor (L 1 ) of the pincushion transformer (T 2 ). Parabolic current amplifying unit to be transmitted to the (a) and the pin switching unit to change the amplification degree according to the mode switching signal input differently according to the horizontal frequency and transmit to the primary reactor (L 1 ) of the pincushion transformer (T 2 ) B) and a current amplifying part (C) that amplifies the current applied from the ABL terminal of the secondary side of the flyback transformer T 1 and applies it to the primary reactor L 1 of the pincushion transformer T 2 . Screen distortion correction circuit, characterized in that the.
KR2019860017014U 1986-11-03 1986-11-03 Picture distortion compensating circuit KR910005344Y1 (en)

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Application Number Priority Date Filing Date Title
KR2019860017014U KR910005344Y1 (en) 1986-11-03 1986-11-03 Picture distortion compensating circuit

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Application Number Priority Date Filing Date Title
KR2019860017014U KR910005344Y1 (en) 1986-11-03 1986-11-03 Picture distortion compensating circuit

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KR880010964U KR880010964U (en) 1988-07-29
KR910005344Y1 true KR910005344Y1 (en) 1991-07-22

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