KR910005115U - Slew rate adjustable tri-state output buffer - Google Patents

Slew rate adjustable tri-state output buffer

Info

Publication number
KR910005115U
KR910005115U KR2019890012812U KR890012812U KR910005115U KR 910005115 U KR910005115 U KR 910005115U KR 2019890012812 U KR2019890012812 U KR 2019890012812U KR 890012812 U KR890012812 U KR 890012812U KR 910005115 U KR910005115 U KR 910005115U
Authority
KR
South Korea
Prior art keywords
output buffer
slew rate
state output
rate adjustable
adjustable tri
Prior art date
Application number
KR2019890012812U
Other languages
Korean (ko)
Other versions
KR940005873Y1 (en
Inventor
이희연
Original Assignee
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사 filed Critical 금성일렉트론 주식회사
Priority to KR2019890012812U priority Critical patent/KR940005873Y1/en
Publication of KR910005115U publication Critical patent/KR910005115U/en
Application granted granted Critical
Publication of KR940005873Y1 publication Critical patent/KR940005873Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
KR2019890012812U 1989-08-31 1989-08-31 Slewrate control tri-state output buffer KR940005873Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019890012812U KR940005873Y1 (en) 1989-08-31 1989-08-31 Slewrate control tri-state output buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019890012812U KR940005873Y1 (en) 1989-08-31 1989-08-31 Slewrate control tri-state output buffer

Publications (2)

Publication Number Publication Date
KR910005115U true KR910005115U (en) 1991-03-20
KR940005873Y1 KR940005873Y1 (en) 1994-08-26

Family

ID=19289633

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019890012812U KR940005873Y1 (en) 1989-08-31 1989-08-31 Slewrate control tri-state output buffer

Country Status (1)

Country Link
KR (1) KR940005873Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100511824B1 (en) * 1997-06-27 2005-11-22 소니 일렉트로닉스 인코포레이티드 Apparatus and method of providing a programmable slew rate control output driver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100511824B1 (en) * 1997-06-27 2005-11-22 소니 일렉트로닉스 인코포레이티드 Apparatus and method of providing a programmable slew rate control output driver

Also Published As

Publication number Publication date
KR940005873Y1 (en) 1994-08-26

Similar Documents

Publication Publication Date Title
DE68912277D1 (en) Output buffer circuit.
DE69028261D1 (en) Optimized input and output buffers
KR890017426U (en) buffer
DE69118953T2 (en) Buffer circuit
BR9005799A (en) ADJUSTABLE CHAIR
DE69317213T2 (en) Output buffer circuits
IL95576A0 (en) Controlled slew rate buffer
DE69216773D1 (en) Output buffer circuit
DE69101371T2 (en) Adjustable delay arrangement.
DE69129729D1 (en) FIFO buffer
DE69115551D1 (en) Buffer circuit
DE69122906T2 (en) FIFO buffer
DE69029054D1 (en) Output device
DE69224572D1 (en) Regulated BICMOS output buffer circuit
DE69028424D1 (en) Output device
DE69029505D1 (en) Output device
DE69223676D1 (en) Output buffer circuit
DE69107432T2 (en) Adjustable delay arrangement.
KR910005115U (en) Slew rate adjustable tri-state output buffer
KR910005113U (en) Slew rate adjustable output buffer
DE69129128D1 (en) Output device
DE69210693D1 (en) Adjustable delay arrangement
FI98565B (en) buffer Volume
DE59108506D1 (en) Output buffer amplifier
KR910005114U (en) Output buffer

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20040719

Year of fee payment: 11

EXPY Expiration of term