KR910004317B1 - Semiconductor device and its manufacturing method for high voltage - Google Patents

Semiconductor device and its manufacturing method for high voltage Download PDF

Info

Publication number
KR910004317B1
KR910004317B1 KR1019880007208A KR880007208A KR910004317B1 KR 910004317 B1 KR910004317 B1 KR 910004317B1 KR 1019880007208 A KR1019880007208 A KR 1019880007208A KR 880007208 A KR880007208 A KR 880007208A KR 910004317 B1 KR910004317 B1 KR 910004317B1
Authority
KR
South Korea
Prior art keywords
region
etching
field
limiting ring
field limiting
Prior art date
Application number
KR1019880007208A
Other languages
Korean (ko)
Other versions
KR900001029A (en
Inventor
김종오
김진형
Original Assignee
현대전자산업 주식회사
정몽헌
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 현대전자산업 주식회사, 정몽헌 filed Critical 현대전자산업 주식회사
Priority to KR1019880007208A priority Critical patent/KR910004317B1/en
Priority to US07/364,624 priority patent/US5003372A/en
Priority to JP14857689A priority patent/JPH0715988B2/en
Publication of KR900001029A publication Critical patent/KR900001029A/en
Application granted granted Critical
Publication of KR910004317B1 publication Critical patent/KR910004317B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched

Abstract

A semiconductor device with a field plate on a main junction area, a field limiting ring area and floating electrodes, has etched grooves formed in the main junction area. An insulating layer is formed on the inside and outside of the etched groove formed in the field plate area and on the inside of the etched groove in the field limiling ring area. The electrodes connected to the main junction are formed on the etched grooves formed in the field plate area. The floating electrodes are formed on the etched grooves formed in the field limiting ring area to provide a high breakdown voltage to the device.

Description

고전압용 반도체 소자 및 그 제조방법High voltage semiconductor device and manufacturing method thereof

제 1 도는 종래의 필드 리미팅 링구조와 필드 플레이트 구조를 조합하여 구성시킨 고전압용 반도체 소자 및 제조방법1 is a high voltage semiconductor device and method for fabricating a combination of a conventional field limiting ring structure and a field plate structure.

제 2 도는 본 발명에 따른 고전압용 반도체 소자 및 그 제조방법2 is a high voltage semiconductor device and a method of manufacturing the same according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 전극 2 : 유리(GLASS)1: electrode 2: glass (GLASS)

3 : P+확산영역 4 : N-에피텍셜 성장층3: P + diffusion region 4: N-epitaxial growth layer

5 : N+기판5: N + substrate

본 발명은 고전압용 반도체 소자 및 그 제조방법에 관한 것으로, 특히 종래의 필드 플레이트 기술구성과 필드 리미팅 링 기술구성을 반도체 에칭기술에 의해 효과적으로 합체구성시켜 반도체 소자의 기능면적을 효과적으로 줄이면서, 더욱 큰 전압을 블로킹할 수 있는 고전압용 반도체 소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage semiconductor device and a method of manufacturing the same. In particular, the conventional field plate technology and the field limiting ring technology are effectively combined by a semiconductor etching technology, thereby effectively reducing the functional area of the semiconductor device, A high voltage semiconductor device capable of blocking voltage and a method of manufacturing the same.

종래의 필드 플레이트와 필드 리미팅 링의 복합 구조에서는 반도체 기판과 반대형의 물질을 주입시키는데, 주접합의 외곽은 두꺼운 유리로 일정한 길이만큼 필드 플레이트를 형성시켜 주접합과 연결되는 전극을 필드 플레이트 위에 형성시키고, 필드 리미팅 링영역은 확산 방식을 이용하여 반도체의 기판과 반대형 물질(주접합과는 동일형 물질)을 형성시켜 부상된 전극을 형성시키는 기술로 고전압용 반도체 소자를 제조하였다.In the conventional structure of the field plate and the field limiting ring, a material opposite to the semiconductor substrate is injected. The outer junction of the main junction is thick glass, and the field plate is formed to a certain length to form an electrode connected to the main junction on the field plate. In the field limiting ring region, a high voltage semiconductor device was manufactured by forming a floating electrode by forming a material opposite to a semiconductor substrate (the same material as a main junction) using a diffusion method.

그러나, 이러한 종래의 필드 플레이트와 필드 리미팅 링 복합기술에서는 고전압용 반도체소자를 제조할 경우 많은 면적이 소요되고 필드 리미팅 링의 갯수가 많아지므로 이에 대한 설계가 매우 어려운 문제점이 있으며, 그에 대한 비용도 많이 드는 단점이 있었다.However, in the conventional field plate and field limiting ring hybrid technology, when manufacturing a high voltage semiconductor device, a large area is required and the number of field limiting rings increases, so the design thereof is very difficult. There was a disadvantage.

따라서, 본 발명의 목적은 종래의 주접합의 외곽의 필드 플레이트영역과 필드 리미팅 링영역을 반도체 에칭기술을 이용하여 홈을 형성하여 합체한 구조로서, 홈 내부에 절연막인 유리층을 형성시킨 다음, 필드 플레이트영역 부분에 형성된 홈에는 플레이트는 주접합과 연결된 전극을 형성시키고 필드 리미팅 링영역 부분에 형성된 홈에는 부상전극을 형성시켜 고전압 능력을 향상시킨 고전압용 반도체 소자 및 그 제조방법을 제공하기 위한 것으로 즉 종래의 필드 플레이트영역 일부와 필드 리미팅 링영역을 반도체 에칭기술을 이용하여 원하는 깊이만큼 에칭시켜서 홈을 형성하고, 상기 필드 플레이트영역 부분에 형성된 홈의 내부와 외부에, 필드 리미팅 링영역 부분에 형성된 홈의 내부에 절연성이 좋은 유리로 채운 다음, 상기 필드 플레이트영역 부분은 주접합과 같은 전극을, 필드 리미팅 링영역 부분은 부상된 전극을 형성시켜서 유리에 의한 전압 블로킹 능력을 부가시켰다.Accordingly, an object of the present invention is to integrate a field plate region and a field limiting ring region of a conventional main junction by forming a groove by using semiconductor etching technology, forming a glass layer as an insulating film inside the groove, and then In order to provide a high voltage semiconductor device and a method of manufacturing the same, the plate is formed in the groove formed in the plate region portion to form an electrode connected to the main junction and the floating electrode is formed in the groove formed in the field limiting ring region portion. A portion of the field plate region and the field limiting ring region of the related art are etched to a desired depth using a semiconductor etching technique to form grooves, and grooves formed in the field limiting ring region portion inside and outside the groove formed in the field plate region portion. The inside of the field plate is filled with good insulating glass, and then Min added an electrode, such as a main junction, and a field limiting ring region portion to form a floating electrode, adding the ability of voltage blocking by the glass.

따라서, 상기 필드 플레이트영역은 에칭홈의 주변 길이에 의하여 평탄면의 필드 플레이트의 길이가 효과적으로 줄어들게 되며, 필드 리미팅 링영역이던 부분 유리에 의하여 전계를 완화시켜서 종래 기술보다 전압블로킹 효과를 더 증대시켰으며, 상기 에칭홈의 형태는 종래의 필드 리미팅 링의 특성과 동일하게 효과적으로 수행하게 되고, 종래처럼 확산방석에 의한 필드 리미팅 링의 형성이 아니므로 설계조건이 종래보다 훨씬 단순하게 설계될 수 있다.Therefore, the length of the field plate of the flat surface is effectively reduced by the peripheral length of the etching groove, and the voltage blocking effect is further increased than the prior art by mitigating the electric field by the partial glass which was the field limiting ring region. In addition, the shape of the etching groove is effectively performed in the same manner as the characteristics of the conventional field limiting ring, and since the field limiting ring is not formed by diffusion cushion as in the related art, the design conditions can be designed much simpler than the conventional one.

본 발명에 의하면, 상기 주접합의 외곽의 필드 플레이트영역 일부와 필드 리미팅 링영역 부위를 반도체 에칭기술을 이용하여 에칭홈을 형성시키고, 상기 필드 플레이트영역은 홈의 내부와 외부에, 필드 리미팅 링영역으로 작용하는 홈의 내부에는 절연막인 유리를 형성한 후, 상기 필드 플레이트영역에 형성된 에칭홈상에는 주접합부와 같은 전극을 형성시키고 상기 필드 플레이트영역 부분에 형성된 에칭홈상에는 부상전극이 형성되도록 구성한 것을 특징으로 한다.According to the present invention, an etching groove is formed in a portion of the field plate region and the field limiting ring region outside the main junction by using a semiconductor etching technique, and the field plate region is a field limiting ring region inside and outside the groove. After forming the glass which is an insulating film in the groove to be operated, an electrode such as a main junction portion is formed on the etching groove formed in the field plate region, and a floating electrode is formed on the etching groove formed in the field plate region portion. do.

또한, 본 발명에 의하면, 상기 필드 플레이트영역의 일부를 에칭시키고, 필드 리미팅 링영역 부위를 P+확산영역의 깊이와 동일한 깊이로 에칭시켜 홈을 형성하는 공정과, 상기 도핑된 유리 층상에 전극을 형성하는 공정과, 상기 다수의 에칭홈들간의 경계지점에 형성된 전극을 소정 간격만큼 에칭하여 부상전극을 형성시키는 공정으로 이루어진 것을 특징으로 한다.Further, according to the present invention, a process of etching a portion of the field plate region, etching the field limiting ring region portion to the same depth as the P + diffusion region, and forming a groove, and forming an electrode on the doped glass layer And etching the electrodes formed at the boundary points between the plurality of etching grooves by a predetermined interval to form floating electrodes.

이하 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 1 도는 종래의 필드 플레이트 구조와 필드 리미팅 링의 구조를 조합하여 구성시킨 고전압용 반도체 소자의 제조기술로서, 애노드가 설치된 N+기판(5)위에 N-에피텍셜 성장층(4)을 성장시키고, 이 에피텍셜 성장층(4)에 P+확산영역(3)을 도면과 같이 형성시킨 다음, 절연막인 유리(2)를 도면에 도시된 바와 같이 형성한다.1 is a manufacturing technique of a high voltage semiconductor device constructed by combining a structure of a conventional field plate structure and a field limiting ring, wherein an N-epitaxial growth layer 4 is grown on an N + substrate 5 provided with an anode, P + diffusion region 3 is formed in the epitaxial growth layer 4 as shown in the figure, and then glass 2 as an insulating film is formed as shown in the figure.

그리고 P+확산영역(3)을 에피텍셜 성장층(4)의 표면까지, 에칭하여 제거한 후 전극(1)을 도면과 같이 형성하여 주접합부를 형성하였다. 한편, 주접합부의 외곽에 형성된 필드 리미팅 링의 영역상의 유리(2)층내의 "F"부분은 소정깊이 "G"만큼 에칭하여 제거하여 고전압용 반도체 소자를 제조하였다.After the P + diffusion region 3 was removed by etching to the surface of the epitaxial growth layer 4, the electrode 1 was formed as shown in the drawing to form a main junction. On the other hand, the "F" portion in the glass 2 layer on the area of the field limiting ring formed on the outer side of the main junction portion was removed by etching by a predetermined depth "G" to manufacture a semiconductor device for high voltage.

그런데, 제 1 도의 종래의 필드 리미팅 링의 구조에서는 반도체 확산방식에 의해 제조하였으므로 소정의 고전압용으로는 적합하지 않으며 고전압의 안정도에도 문제가 있었다. 필드 리미팅 링의 수를 많이 형성하여야 했으므로, 이에 따른 제조공정이나 경비가 많이 소요되어야만 했다.By the way, in the structure of the conventional field limiting ring of FIG. 1, it is manufactured by the semiconductor diffusion method, which is not suitable for a predetermined high voltage, and also has a problem of high voltage stability. Since a large number of field limiting rings had to be formed, a lot of manufacturing processes and expenses were required.

따라서, 본 발명에서 항복전압을 보완하기 위하여 종래에 주접합부의 외곽 필드 플레이트영역과 필드 리미팅 링의 P+확산영역을 주접합부의 P+확산영역과 동일 깊이로 에칭하여 홈을 형성시키고 그 위에 도핑되는 유리에 의하여 전계를 완화시켜 종래보다 더 큰 고전압을 블로킹할 수 있도록 구성하고 또한 종래에는 필드 리미팅 링을 P+확산 처리하였지만 본 발명에서는 실리콘 에칭처리로 간단히 수행하여 더 큰 효과를 낼 수 있는 것으로, 이하 제 2 도에서 상세히 설명키로 한다.Therefore, in order to compensate for the breakdown voltage in the present invention, the outer field plate region of the main junction portion and the P + diffusion region of the field limiting ring are conventionally etched to the same depth as the P + diffusion region of the main junction portion to form a groove and doped thereon. By mitigating the electric field by blocking the higher voltage than the conventional, and in the conventional field limiting ring P + diffusion process, but in the present invention can be performed simply by silicon etching treatment to achieve a greater effect. It will be described in detail in FIG.

제 2 도는 본 고안에 따른 고전압용 반도체 소자의 구성도로서, 애노드가 설치된 N+기판(5)위에 N-에피텍셜 성장층(4)을 성장시키고, 도면에서 점선으로 도시된 바와 같이 상기 N-에피텍셜 성장층(4)에는 P+확산영역(3)을 형성시킨다. 그 다음 "C"부분과 "D"부분을 P+확산영역(3)의 깊이와 동일하게 에칭시킨 후 유리(2)를 일정한 두께로 도핑시키는 한편, "B"부분은 P+확산영역(3)의 표면까지 제거시켜 주접합부를 형성시킨 다음 상기 유리(2)층위에 일정한 두께로 전극(1)을 형성시킨다. 여기에서 "B"부분에 형성된 전극(1)층상에 캐소드를 설치하는 한편, 에칭 처리된 필드 플레이트영역인 "C"부분과 필드 리미팅 링영역이었던 "D"부분의 경계지점인 "E"부분의 전극(1)층을 에칭처리로 제거하여 "D"부분에 형성된 에칭홈상에는 부상전극이 형성되도록 구성한 고전압용 반도체 소자를 제조 구성하였다.FIG. 2 is a schematic diagram of a semiconductor device for high voltage according to the present invention, in which an N-epitaxial growth layer 4 is grown on an N + substrate 5 having an anode, and the N-epi as shown by a dotted line in the figure. P + diffusion region 3 is formed in the textural growth layer 4. The "C" and "D" sections are then etched to the same depth as the P + diffusion region 3 and then the glass 2 is doped to a constant thickness, while the "B" portion of the P + diffusion region 3 The main junction is removed by removing the surface, and then the electrode 1 is formed to a predetermined thickness on the glass 2 layer. Here, the cathode is provided on the electrode 1 layer formed at the "B" portion, while the "C" portion, which is the etched field plate region, and the "E" portion, which is the boundary point of the "D" portion, which was the field limiting ring region. A high voltage semiconductor device was fabricated so that the floating electrode was formed on the etching groove formed in the "D" portion by removing the electrode 1 layer by etching.

이러한 본 발명의 구조에 의하여, 종래의 필드 플레이트영역은 에칭시킨 홈의 주변 깊이에 의하여 필드 플레이트 길이를 효과적으로 줄일 수 있고, 필드 리미팅 링영역에 형성된 에칭홈은 전계를 완화시킴에 따라 유리에 의한 블로킹 전압이 부가되어 더 높은 항복전압을 가질 수 있었다.According to the structure of the present invention, the conventional field plate region can effectively reduce the length of the field plate by the peripheral depth of the etched groove, and the etching groove formed in the field limiting ring region blocks the glass by relaxing the electric field. The voltage could be added to have a higher breakdown voltage.

따라서, 본 발명의 기술을 이용할 경우 종래 기술인 필드 플레이트와 필드 리미팅 링영역의 단순한 복합구조보다 상대적으로 매우 큰 항복전압을 설계할 수 있어 그에 따른 설계비용이 대폭 감소됨과 동시에 반도체 기판 설계가 용이하게 되며, 이는 수직 이중-확산된 MOSFET(VERTICAL DOUBLE-DIFFUSED MOSFET)의 설계시 기판의 저항 성분을 줄이게 됨으로써 전체적인 ON-RESISTANCE를 줄이게 되어, 전류를 상대적으로 증가시키는 요인이 되며, 이는 매우 개선된 칩 사이즈(CHIP SIZE)에서 고전압/고전류의 소자를 형성할 수 있게 된다.Therefore, when using the technique of the present invention it is possible to design a breakdown voltage that is relatively much larger than the simple composite structure of the field plate and the field limiting ring region of the prior art, thereby significantly reducing the design cost and easy to design the semiconductor substrate This reduces the overall resistivity of the substrate in the design of vertical double-diffused MOSFETs, which reduces the overall ON-RESISTANCE, resulting in a relatively increased current, which is a very improved chip size. In the chip size, it is possible to form a high voltage / high current device.

Claims (3)

필드 플레이트와 필드 리미팅 링의 복합구조에서, 주접합부 상에 일정한 유리막으로 필드 플레이트를 형성시키고, 필드 리미팅 링영역은 반도체 확산 방식을 이용하여 반도체의 기판과 반대형 물질을 형성시켜 부상전극을 형성시키는 구조로 이루어진 고전압용 반도체 소자에 있어서, 상기 주접합부의 필드 플레이트영역 일부와 필드 리미팅 링영역 부분을 반도체 에칭기술을 이용하여 에칭홈을 형성시키고, 상기 필드 플레이트영역부분에 형성된 에칭홈은 내부와 외부에, 필드 리미팅 영역부분에 형성된 에칭홈은 내부에 절연막인 유리를 형성한 후, 상기 필드 플레이트상의 홈에는 주접합부와 같은 전극을 형성시키고 필드 리미팅 영역부분에 형성된 에칭홈상에는 부상전극이 형성되도록 구성한 것을 특징으로 하는 고전압용 반도체 소자.In the composite structure of the field plate and the field limiting ring, a field plate is formed with a constant glass film on the main junction, and the field limiting ring region forms a material opposite to the substrate of the semiconductor using a semiconductor diffusion method to form floating electrodes. In a high voltage semiconductor device having a structure, an etching groove is formed in a part of the field plate region and a field limiting ring region of the main junction by using a semiconductor etching technique, and the etching grooves formed in the field plate region are formed inside and outside. In the etching grooves formed in the field limiting region, glass is formed as an insulating film therein, and the grooves on the field plates are formed with the same electrode as the main junction and the floating electrodes are formed on the etching grooves formed in the field limiting region. A high voltage semiconductor device, characterized in that. 제 1 항에 있어서, 상기 에칭홈의 에칭 깊이는 주접합부의 P+확산영역과 동일한 깊이로 에칭되고, 각각 동일 크기인 것을 특징으로 하는 고전압용 반도체 소자.The semiconductor device for high voltage according to claim 1, wherein the etching depth of the etching groove is etched to the same depth as the P + diffusion region of the main junction portion, and is the same size. N+기판상에 N-에피텍셜 성장층을 형성시켜, 주접합부의 필드 리미팅 링영역상에 P+확산처리하는 공정과, 상기 P+확산처리된 주접합부 및 필드 리미팅 링영역상에 절연체인 유리를 형성하는 공정과, 상기 형성된 유리층의 주접합부상 필드 플레이트 일부는 N-에피텍셜 성장층의 표면까지 에칭하여 제거시키고, 필드 리미팅 영역상의 일부는 유리 도핑층의 소정깊이만큼 에칭하여 홈을 구성시키는 공정으로 이루어진 고전압용 반도체 제조방법에 있어서, 상기 필드 플레이트영역의 일부를 에칭시키고, 필드 리미팅 링영역 부분을 P+확산영역의 깊이와 동일한 깊이로 에칭시켜 에칭홈을 형성시키는 공정과, 상기 필드 플레이트의 주접합부 위와 필드 리미팅 링영역에 형성된 에칭홈상에 절연막인 유리를 형성하는 공정과, 상기 도핑된 유리층상에 전극을 일정한 두께로 형성하는 공정과, 상기 에칭홈들간의 경계지점에 형성된 전극층을 소정 간격만큼 에칭하여 부상전극을 형성시키는 공정으로 이루어진 것을 특징으로 하는 고전압용 반도체 제조방법.Forming an N-epitaxial growth layer on the N + substrate to form P + diffusion on the field limiting ring region of the main junction, and forming an insulator glass on the P + diffused main junction and the field limiting ring region. And a part of the field plate on the main junction portion of the formed glass layer is etched and removed to the surface of the N-epitaxial growth layer, and a part of the field limiting region is etched by a predetermined depth of the glass doped layer to form a groove. A method for fabricating a high voltage semiconductor, comprising: etching a portion of the field plate region, etching a portion of the field limiting ring region to a depth equal to the depth of the P + diffusion region, and forming an etching groove; Forming a glass as an insulating film on an etching groove formed in the upper and field limiting ring regions, and applying an electrode on the doped glass layer. Semiconductor production method for a high voltage is etched by a predetermined distance and the process, the electrode layer formed on the boundary between the etching groove formed to a thickness which is characterized by being a step of forming an electrode portion.
KR1019880007208A 1988-06-16 1988-06-16 Semiconductor device and its manufacturing method for high voltage KR910004317B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019880007208A KR910004317B1 (en) 1988-06-16 1988-06-16 Semiconductor device and its manufacturing method for high voltage
US07/364,624 US5003372A (en) 1988-06-16 1989-06-09 High breakdown voltage semiconductor device
JP14857689A JPH0715988B2 (en) 1988-06-16 1989-06-13 High voltage semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880007208A KR910004317B1 (en) 1988-06-16 1988-06-16 Semiconductor device and its manufacturing method for high voltage

Publications (2)

Publication Number Publication Date
KR900001029A KR900001029A (en) 1990-01-31
KR910004317B1 true KR910004317B1 (en) 1991-06-25

Family

ID=19275225

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880007208A KR910004317B1 (en) 1988-06-16 1988-06-16 Semiconductor device and its manufacturing method for high voltage

Country Status (1)

Country Link
KR (1) KR910004317B1 (en)

Also Published As

Publication number Publication date
KR900001029A (en) 1990-01-31

Similar Documents

Publication Publication Date Title
US6291856B1 (en) Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6190948B1 (en) Method of forming power semiconductor devices having overlapping floating field plates for improving breakdown voltage capability
US4974059A (en) Semiconductor high-power mosfet device
CN102194858B (en) Semiconductor device
US8344448B2 (en) Semiconductor device having an edge termination structure and method of manufacture thereof
TW200305970A (en) Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
JPH10341018A (en) Semiconductor device having lateral high breakdown voltage element and fabrication thereof
JP2003273355A (en) Semiconductor element and method for manufacturing the same
CN1379479A (en) Electric semiconductor device
KR20040053339A (en) Trench mosfet device with improved on-resistance
JPH0661497A (en) Semiconductor device and its manufacture
US20080116520A1 (en) Termination Structures For Semiconductor Devices and the Manufacture Thereof
JPH0481345B2 (en)
KR910004317B1 (en) Semiconductor device and its manufacturing method for high voltage
JP2002016250A (en) Semiconductor device and its manufacturing method
CN106876441B (en) Power device with fixed interface charge field limiting ring
JPS58165380A (en) High withstand voltage semiconductor device
CN113990942B (en) LDMOS device with circularly symmetric structure and preparation method thereof
KR101328667B1 (en) Method for manufacturing a trench gate type MOSFET
CN216354226U (en) MOSFET with high carrier mobility
US20090020832A1 (en) Semiconductor Devices and the Manufacture Thereof
JPS61220377A (en) Semiconductor device
TW202345215A (en) Source-body self-aligned method of a vertical double diffused metal oxide semiconductor field effect transistor
KR100275755B1 (en) High power bipolar transistor and method for fabricating thereof
KR100199032B1 (en) Manufacturing method of power device

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060523

Year of fee payment: 16

LAPS Lapse due to unpaid annual fee