KR910003664A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR910003664A
KR910003664A KR1019900000095A KR900000095A KR910003664A KR 910003664 A KR910003664 A KR 910003664A KR 1019900000095 A KR1019900000095 A KR 1019900000095A KR 900000095 A KR900000095 A KR 900000095A KR 910003664 A KR910003664 A KR 910003664A
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South Korea
Prior art keywords
selection
signal
internal
selecting
holding
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KR1019900000095A
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Korean (ko)
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KR970000690B1 (en
Inventor
요우이찌 도비다
Original Assignee
시기 모리야
미쓰비시뎅끼 가부시끼가이샤
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Publication of KR910003664A publication Critical patent/KR910003664A/en
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Publication of KR970000690B1 publication Critical patent/KR970000690B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

내용 없음.No content.

Description

반도체기억장치Semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 이 발명의 한 실시예에 의한 DRAM의 구성을 표시하는 블록도.1 is a block diagram showing the structure of a DRAM according to one embodiment of the present invention;

제2도는 제1도에 표시되는 메모리셀얼레이(셀스앰프+I/0 스위치) 블록 및 Y 디코더의 구성을 표시하는 회로도.FIG. 2 is a circuit diagram showing the configuration of the memory cell array (cell amplifier + I / 0 switch) block and Y decoder shown in FIG.

제3도는 제1도에 표시되는 셀렉터, 입력버퍼, Y 디코더 및 시프트 레지스터의 구성을 표시 하는 회로도.3 is a circuit diagram showing the configuration of the selector, input buffer, Y decoder and shift register shown in FIG.

Claims (2)

행 및 열상에 배열되는 복수의 메모리 셀로써 이루어지는 메모리 셀 얼레이, 외부로부터 부여되는 어드레스 신호에 응답하여, 내부 열 어드레스 신호를 발생하는 내부 어드레스 발생 수단, 상기 내부 어드레스 발생수단으로부터 발생되는 상기 내부 열 어드레스 신호에 응답 하여 상기 메모리셀 얼레이의 복수열을 동시에 선택하기 위한 선택신호를 발생하는 제1의 선택수단, 상기 제1의 선택수단에 의하여 발생된 상기 선택신호를 유지하는 유지수단, 상기 유지수단에 유지된 상기 선택신호에 의하여 동시에 선택된 복수열을 순서적으로 선택하는 제2의 선택수단, 상기 제2의 선택수단에 의하여 선택된 열에 외부로부터의 정보를 부여하는 기록수단, 및 상기 제2의 선택수단에 의한 선택동작의 사이에, 다음의 내부열 어드레스 신 호를 응답하는 상기 제1의 선택수단에 의한 선택동작이 행하여 지도록 타이밍제어를 행하는 타이밍 제어수단을 구비한, 반도체기억장치.A memory cell array comprising a plurality of memory cells arranged in rows and columns, internal address generating means for generating an internal column address signal in response to an address signal provided from the outside, and said internal column address generated from said internal address generating means First selecting means for generating a selection signal for simultaneously selecting a plurality of rows of the memory cell array in response to a signal, holding means for holding the selection signal generated by the first selecting means, and the holding means. Second selection means for sequentially selecting a plurality of columns simultaneously selected by the held selection signal, recording means for giving information from the outside to the columns selected by the second selection means, and the second selection means. The first internal response to the next internal column address signal during the selection operation by " A selection operation by the selection means is performed so that a timing control means for performing timing control, the semiconductor memory device. 행 및 열상으로 배열되는 복수의 메모리 셀로써 이루어지는 메모리 셀 얼레이, 외부로부터 부여되는 어드레스 신호에 응답하여, 내부 열 어드레스 신호를 발생하는 내부 어드레스 발생수단, 상기 내부어드레스 발생수단으로부터 발생되는 상기 내부 열 어드레스 신호에 응답하여, 상기 메모리셀 얼레이의 복수형을 동시에 선택하는 제1의 선택수단, 상기 제1의 선택 수단에 의하여 동시에 선택된 복수열로부터 판독되는 복수의 정보를 유지하는 유지수단, 상기 유지수단에 유지된 상기 복수의 정보를 순서로 선택하는 제2의 선택수단, 및 상기 제2의 선택수단에 의한 선택동작의 사이에, 다음의 내무 열 어드레스 신호에 응답하는 상기 제1의 선택수단에 의한 선택동작이 행하여지도록 타이밍 제어를 행하는 타이밍제어수단을 구비한 반도체기억장치.A memory cell array consisting of a plurality of memory cells arranged in rows and columns, an internal address generating means for generating an internal column address signal in response to an address signal supplied from the outside, and an internal column address generated from the internal address generating means First selecting means for simultaneously selecting a plurality of types of memory cell arrays in response to a signal, holding means for holding a plurality of pieces of information read from a plurality of rows simultaneously selected by the first selecting means, and holding in the holding means A selection operation by the first selection means in response to a next internal column address signal between the second selection means for sequentially selecting the plurality of pieces of information, and a selection operation by the second selection means. A semiconductor memory device comprising timing control means for performing timing control to perform this. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900000095A 1988-08-31 1990-01-05 Semiconductor memory device KR970000690B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP21871588 1988-08-31
JP1-183217 1989-07-14
JP18321789A JPH0713862B2 (en) 1988-08-31 1989-07-14 Semiconductor memory device
JP89-183217 1989-07-14

Publications (2)

Publication Number Publication Date
KR910003664A true KR910003664A (en) 1991-02-28
KR970000690B1 KR970000690B1 (en) 1997-01-18

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KR1019900000095A KR970000690B1 (en) 1988-08-31 1990-01-05 Semiconductor memory device

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JP (1) JPH0713862B2 (en)
KR (1) KR970000690B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69130210T2 (en) * 1990-11-16 1999-01-21 Fujitsu Ltd., Kawasaki, Kanagawa SEMICONDUCTOR MEMORY WITH HIGH-SPEED ADDRESS DECODER

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KR970000690B1 (en) 1997-01-18
JPH02139793A (en) 1990-05-29
JPH0713862B2 (en) 1995-02-15

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