KR910002961B1 - Charging and equalizing circuit for semiconductor memory device - Google Patents

Abstract

In circuit for charging and lighing a bit-line of static ramdom acess memory (SRAM), charging circuit is composed of the first and the second P-MOS transistors (31,32) connected dircctly to between a driving voltage and bit-line. Output purse of address transition detector (ATD) is applied to the gate of these transistors. Lighting circuit includes the third P-MOS transistor (33) connected with parallel to the two terminals of bit-line. Loading circuit is composed of the fourth and the fivth transistors (34,35) connected with parallel to the each of charging circuit.

Description

Charge and Equalization Circuit of Semiconductor Memory Device

1 is a conventional bit line charging and equalization circuit.

2 is a circuit for gate adjustment of a bit line load transistor according to the present invention.

3 is a bit line charging and equalizing circuit according to the present invention.

4 is a timing diagram of a bit line charging and equalizing circuit according to the present invention.

The present invention relates to a charging and equalizing circuit of a semiconductor memory device, and more particularly to a circuit for charging and equalizing a bit line of a static random access memory (SRAM).

In general, a memory cell of a static RAM includes a pair of load means and driving transistors connected in series between a power supply voltage and ground, and a source and a drain are connected between a connection node and a bit line of the load means and driving transistor. And a transfer mode transistor connected to a gate thereof, and the gates of the connection node and the drive mode transistor are connected to each other to form a flip-flop.

Since 64kbit static RAM, an address change detector (hereinafter referred to as ATD) that detects an address signal change and generates a pulse is used for high speed operation and low power consumption. The ATD circuit is installed at the input of each address and takes the logical sum of the outputs and makes an internal pulse signal. When a change occurs in any one of the address inputs, a pulse is generated. Generate. Since the bit line of the static RAM is equalized and precharged to a predetermined voltage level using a pulse of the ATD circuit to perform a read operation or a write operation, data stored in a memory cell can be accessed or stored at a high speed. In addition, since the word line receives an ATD pulse and becomes a high level only for a certain period of time, current flows into the copper plate memory cell, thereby reducing power consumption of the memory cell.

)에 접속된 제1및 제2엔모오스 트랜지스터(1,2)와, 상기 제1및 제2엔모오스 트랜지스터(1,2)의 게이트와 소오스에 각각 드레인과 소오스가 접속되고 게이트에 ATD 회로로 부터 발생되는 펄스

가 인가된 제3 및 제4엔모오스 트랜지스터(3,4)로 구성되는 충전회로(9)와, 상기 전원공급전압과 비트라인 사이에 직렬접속되어 제1게이트에는 상기 전원공급 전압이 인가되고 제2게이트에는 상기 ATD 회로로 부터 발생되는 펄스

가 인가되는 제5, 제7 및 제6, 제8엔모오스 트랜지스터(5,7,6,8)로 구성되는 등화회로(10)로 구성된다.1 is a conventional bit line charge and equalization circuit, in which a power supply voltage Vcc is applied to a gate and a drain, and a source is

And a drain and a source are respectively connected to a gate and a source of the first and second enMOS transistors 1 and 2, and the gate and the source of the first and second enMOS transistors 1 and 2, respectively. Pulses from

A charging circuit 9 including third and fourth NMOS transistors 3 and 4 to which the first and fourth nMOS transistors 3 and 4 are applied, and the power supply voltage is connected in series between the power supply voltage and the bit line. 2 gates have a pulse generated from the ATD circuit

And an equalization circuit 10 composed of fifth, seventh, sixth, and eighth MOS transistors 5, 7, 6, and 8 to which n is applied.

가 모두 하이레벨이 되므로 상기 충전회로(9)의 제1, 제2, 제3, 제4엔모오스 트랜지스터(1,2,3,4)와 상기 등화회로(10)의 제5, 제6, 제7, 제8엔모오스 트랜지스터(5,6,7,8)이 모두 턴온(Tum-On) 상대가 된다. 그리하여 리드동작 또는 라이트 동작을 하기전에 상기 비트라인을 소정을 전압레벨로 충전 및 등화시킨다.If a pulse is generated from the ATD circuit due to a change in address, the

Are all at the high level, so that the first, second, third and fourth NMOS transistors 1, 2, 3, and 4 of the charging circuit 9 and the fifth, sixth, and The seventh and eighth NMOS transistors 5, 6, 7, and 8 are all turned on. Thus, the bit line is charged and equalized to a predetermined voltage level before the read operation or the write operation.

In general, during the read operation, the read operation is performed immediately after the word line becomes a high level by the ATD pulse. When the read operation is finished, the word line is disabled. This reduces the power consumption by blocking the bit line current from the bit line to the memory cell.

On the other hand, since the write operation is to write information from the outside, the word line must be enabled at all times.

가 로우상태이므로 상기 제3, 제4, 제7 및 제8엔모오스 트랜지스터(3,4,7,8)가 턴오프(Turn-off)가 되고 상기 제1 및 제2엔모오스 트랜지스터(1,2)는 턴온된다. 따라서 라이트 동작시에는 비트라인 전류가 전적으로 상기 제1 및 제2엔모오스 트랜지스터(1,2)의 구동능력에 의존하며, 상기 제1 및 제2엔모오스 트랜지스터(1,2)에 의해 비트라인 누설전류가 보상된다. 통상적으로 비트라인 누설전류는 수십 피코암페어(Pico ampere)정도이므로 상기 제1 및 제2엔모오스 트랜지스터(1,2)의 구동능력을 크게 줄이더라도 비트라인 누설전류를 보상하기에는 충분하다.Typically pulse during write operation

Since the third, fourth, seventh and eighth NMOS transistors 3, 4, 7, 8 are turned off, and the first and second NMOS transistors 1, 2) is turned on. Therefore, in the write operation, the bit line current is entirely dependent on the driving capability of the first and second NMOS transistors 1 and 2, and the bit line leakage is caused by the first and second ENMOS transistors 1 and 2. The current is compensated. In general, since the bit line leakage current is about tens of pico ampere, it is sufficient to compensate for the bit line leakage current even if the driving capability of the first and second enMOS transistors 1 and 2 is greatly reduced.

As can be seen from the above description, in the conventional bit line charging and equalizing circuit, the bit line current is reduced as much as possible in order to reduce the power consumption of the memory cell during write operation, while at the same time, at least to compensate for the leakage current of the bit line. There is no method other than the method of adjusting the sizes of the first and second enMOS transistors 1 and 2 so that only a current of the electric current can flow.

In order to reduce the bit line current, both the method of narrowing the channel width and the channel length of the first and second NMOS transistors 1 and 2 are used. In narrowing the channel width, since there is a resolution limit of the mask pattern during the photolithography process, it is impossible to narrow the channel width below the limit value. Therefore, the channel length must be increased for a certain channel width. However, when the channel length is increased, an area occupied by the first and second enMOS transistors 1 and 2 increases. That is, a static RAM memory cell requires a bit line charging and equalizing circuit for each bit line pair according to an operation principle. The first and second NMOS transistors 1 and 2 of each bit line charging and equalizing circuit are required. As the area occupied by) increases, the total area of the memory chip is increased so that it cannot meet the trend of high integration and miniaturization.

In addition, since the bit line is charged and equalized from the low level to the high level in the read operation after the write operation, there is a problem in that the peak current is large.

Accordingly, an object of the present invention is to provide a bit line charging and equalizing circuit capable of compensating for bit line leakage current while at the same time minimizing the bit line current without increasing the area in the bit line charging and equalizing circuit of a semiconductor memory device. Is in.

Another object of the present invention is to provide a bit line charging and equalizing circuit which reduces peak current during a read operation after a write operation in a bit line charging and equalizing circuit of a semiconductor memory device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit for adjusting the gate voltage of a bit line load transistor according to the present invention.

As shown in FIG. 2, inverting means 11 for inverting and outputting the XWE signal by inputting the write enable signal XWE, buffer means 12 for buffering the XWE signal, and inverting means (11) and a pulse connected between the output of the buffer means 12 and the bit line charging and equalizing circuit 30 to generate a pulse V _WEBL controlling the gate of the load transistor of the bit line charging and equalizing circuit 30. It consists of the generating means 20. Here, the inverting means (11) and the buffer means is composed of the CMOS inverter. The pulse V _WEBL is an input signal of each bit line charging and equalizing circuit BL1, BL2, ... BLn connected to each memory cell of the memory cell array 13.

In addition, the pulse generating means 20 is a gate input to the output of the inverting means 11, the drain is connected to the power supply voltage, the first NMOS transistor 21 and the output of the buffer means 12 gates A voltage drop connected in parallel with the second NMOS transistor 22 and a second NMOS transistor 22 connected in series with the first NMOS transistor 21 and a power supply voltage applied to a gate thereof. The third NMOS transistor 23 is formed.

3 is a bit line charging and equalization circuit diagram in accordance with the present invention.

의 반전상태

WE 펄스를 게이트 입력으로 하고 전원공급 전압과 비트라인(BL,BL) 사이에 소오스와 드레인이 접속되어 상기 비트라인을 충전하기 위한 제1 및 제2피모오스 트랜지스터(31,32)와, 상기

WE 펄스를 게이트 입력으로 하고 상기 비트라인 쌍 사이에 접속되어 상기 비트라인 쌍을 등화하기 위한 제3피모오스 트랜지스터(33)와, 상기 제1 및 제2피모오스 트랜지스터(31,32)와 병렬접속되고 상기 펄스 발생수단(20)의 출력신호 V_WEBL을 게이트 입력으로 하는 제4 및 제5 부하용 피모오스 트랜지스터(34,35)로 비트라인 충전 및 등화회로(30)를 구성한다.Pulses from ATD Circuit

Inversion of

First and second PMOS transistors 31 and 32 for charging the bit line by connecting a source and a drain between the power supply voltage and the bit lines BL and BL with the WE pulse as a gate input;

A third PMOS transistor 33 for equalizing the bit line pair, connected between the bit line pairs with a WE pulse as a gate input, and in parallel with the first and second PMOS transistors 31 and 32. The bit line charging and equalizing circuit 30 is constituted by the fourth and fifth load PMOS transistors 34 and 35 having the output signal V _WEBL of the pulse generating means 20 as a gate input.

The same numbers as those in FIG. 2 are used. Here, the bit line charging and equalizing circuit 30 is connected to one memory cell 14 connected between the word line WL and the bit line, and the memory cell 14 is a known static RAM circuit.

이며, 상기 제4(C)도는 상기 제2도의 비트라인 부하 트랜지스터의 게이트 조정회로의 출력펄스 V_WEBL이고, 상기 제4(D)도는 ATD로 부터 발생되는 비트라인 등화펄스

이며 상기 제4(E)도는 비트라인의 상태를 나타내는 파형도이다.4 (A)-(E) are timing diagrams according to the present invention. The fourth (A) is an address signal, and the fourth (B) is a read operation in a high state and a write in a low state. Light enable signal to activate

4C is an output pulse V _WEBL of the gate adjustment circuit of the bit line load transistor of _FIG . 2, and _FIG . 4D is a bit line equalization pulse generated from ATD.

4E is a waveform diagram showing the state of the bit line.

Hereinafter, the second and third non-degree operation relations will be described in detail with reference to the timing diagram of FIG. 4.

가 하이상태에서 로우상태로 천이하여 상기 로우상태의 XEW 펄스가 상기 제2도의 반전수단(11)과 버퍼수단(12)으로 입력된다.When the address signal of FIG. 4A changes in time t1, the write enable signal of FIG. 4B is changed.

Transitions from the high state to the low state, and the XEW pulse of the low state is input to the inverting means 11 and the buffer means 12 of FIG.

Thus, signals opposite to each other are input to the gates of the first and second NMOS transistors 21 and 22 of the pulse generating means 20. That is, the first NMOS transistor 21 is turned on by the gate input in the high state, and the second NMOS transistor 22 is turned off by the gate input in the low state.

Meanwhile, in order for the fourth and fifth PMOS transistors 34 and 35 of the bit line charging and equalizing circuit 30 of FIG. 3 to be turned on, the gate voltage V _WEBL is VCC-V _TP (V _TP is _PMOS ). Operation must be smaller than the threshold level of the transistor).

Vcc-｜V_TP｜로 부터 V_D23의 조건을 다음과 같다. 즉 V_D23

｜V_TP｜-V_TN'의 조건을 만족하도록 상기 제3엔모오스 트랜지스(23)의 크기를 결정하여 비트라인 부하트랜지스터의 게이트를 조정한다. (V_TN' 은 엔모오스 트랜지스터의 보다 효과(Body Effect)를 고려한 드레쉬 홀드 레벨임)In order to satisfy the conditions as described above, a third NMOS transistor having a gate connected to a power supply voltage between a connection node point WE _BL ground of the first and second NMOS transistors 21 and 22 in FIG. Connect 23) in parallel. If the claim is not a three-en Mohs transistor 23 is V _WEBL = Vcc-V _TN 'and transistor 23 is available as it is no voltage drop by the drain Threshold voltage i.e. V _D23 of the transistor 23, V _WEBL = Vcc-V _TN '-V _D23 . This satisfies the requirement that the voltage level of V _WEBL be less than Vcc-V _TP . Vcc-V _TP '-V _D23

The conditions of V _D23 from Vcc- | V _TP | are as follows. V _D23

The gate of the bit line load transistor is adjusted by determining the size of the third NMOS transistor 23 so as to satisfy the condition of | V _TP | -V _TN '. (V _TN 'is the threshold hold level considering the Body Effect of the EnMOS transistor.)

As a result, at the time t1, the fourth and fifth PMOS transistors 34 and 35 of FIG. 3 are turned on.

가 발생하여 상기

펄스가 로우상태일 때, 즉 실제로라이트 동작이 수행되는 t3시간에서 t5시간 동안 비트라인 누설전류를 보사할 수 있는 정도의 전류를 흘리게 됨으로써 라이트 사이클시의 동작전류를 줄일 수 있다. t4시간에서 라이트 인에이볼신호

가 반전되면 WE_BL의 전압은 상기 제2도의 제2엔모오스 트랜지스터(22)의 턴온에 의해 급속히 로우레벨로 천이되고, 그에 따라 상기 제4 및 제5트랜지스터(34,35)를 완전히 온시킴으로써 비트라인을 1차적으로 등화시키게 된다. 그후 t5시간에

펄스를 상기 제1, 제2 및 제3피모오스 트랜지스터(31,32,33)에 인가하여 상기 트랜지스터들을 턴온시킴에 의해 상기 비트라인 쌍의 충전 및 등화를 마무리지어 다음 리드동작을 수행한다.Thus a pulse from the ATD circuit at t2 hours

Caused by

When the pulse is in a low state, that is, a current capable of compensating for the bit line leakage current for t5 hours from t3 time at which the write operation is actually performed, the operating current during the light cycle can be reduced. Light enable signal at t4 hours

When is inverted, the voltage of WE _BL is rapidly shifted to the low level by the turn-on of the second NMOS transistor 22 in FIG. 2, thereby turning on the fourth and fifth transistors 34 and 35 completely. The line is first equalized. Then t5 hours

A pulse is applied to the first, second and third PMOS transistors 31, 32, and 33 to turn on the transistors to finish charging and equalizing the pair of bit lines to perform the next read operation.

펄스가 들어오기 전까지 리드동작을 수행하고, t2시긴에서

펄스가 인가되면, 상기 제1, 제2, 제3, 제4 및 제5피모오스 트랜지스터(31, 32, 33, 34, 35)가 턴온됨으로써 라이트 동작전 비트라인을 미리 Vcc레벨로 충전 및 등화시키게 된다. 그 후 라이트 동작시에는 로우상태의

에 의해 V_WEBL이 Vcc-V_TN'-V_D23외 레벨로 되어 상기 제4 및 제5피모오스 트랜지스타(34,35)가 턴온되는 시점에 있게 되고 로우상태의

펄스에 의해 상기 제1, 제2 및 제3피모오스 트랜지스턴(31,32,33)은 턴오프됨으로써 상기 제4 및 제5피모오스 트랜지스터(34,35)에 의해 비트라인 누설전류를 보상할 수 있을 정도의 최소한 비트전류를 비트라인에 공급하게 된다.In other words, even if the address signal changes at time t1 and the write signal comes in, at time t2

Perform read operation until the pulse comes in, and at t2

When a pulse is applied, the first, second, third, fourth, and fifth PMOS transistors 31, 32, 33, 34, and 35 are turned on to charge and equalize the bit line to the Vcc level before the write operation. Let's go. After that, during the light operation,

V _WEBL is brought to a level other than Vcc-V _TN '-V _D23 so that the fourth and fifth PMOS transistors 34 and 35 are turned on and are in a low state.

The first, second and third PMOS transistors 31, 32 and 33 are turned off by a pulse to compensate for the bit line leakage current by the fourth and fifth PMOS transistors 34 and 35. Supply as much bit current as possible to the bit line.

신호가 하이상태로 천이함에 의하여 V_WEBL의 레벨이 로우상태로 되어 감에 따라 상기 제4 및 제5피모오스 트랜지스터(34,35)는 완전히 턴온상태가 되어 비트라인의 레벨을 수정레벨로끌어 올림으로써 1차적인 충전 및 등화가 이루어진다.Then at t4 hours

As the level of V _WEBL goes low as the signal transitions to the high state, the fourth and fifth PMOS transistors 34 and 35 are completely turned on to raise the level of the bit line to the crystal level. Primary charging and equalization is achieved.

펄스가 인가되면 상기 제1, 제2, 제3, 제4 및 제5피모오스 트랜스터(31,32,33,34,35)가 모두 턴온됨으로써 비트라인 Vcc레벨로 되어 완전히 충전 및 등화가 이루어진다.Then at t5 hours

When a pulse is applied, the first, second, third, fourth, and fifth pimoth transformers 31, 32, 33, 34, and 35 are all turned on to become the bit line Vcc level to fully charge and equalize. .

As described above, in the bit line charging and equalizing circuit, the present invention _places the voltage V _WEBL applied to the gates of the fourth and fifth PMOS transistors, which are the bit line load transistors, in the write operation, near the threshold hold voltage. By minimizing the line current, the power consumption due to the bit line current is reduced and the bit line leakage current can be compensated for.

In addition, the present invention has the effect of reducing the peak current of the bit line by performing in two stages of charging and equalizing the bit line during the read operation after the write operation. As a result, stable operation of the memory cell can be obtained.

In addition, the present invention has the effect of significantly reducing the area of the memory chip compared to the prior art by tying together and simplifying the function of compensating for bit line leakage current in the bit line charging and equalizing circuit unit. Accordingly, high integration and miniaturization of the device can be easily realized.

Claims (1)

Charging means comprising first and second PMOS transistors 31 and 32 connected in series between the power supply voltage and the bit line and to which the output pulse of the address change detector is applied to the gate and in parallel across the bit line; Equalization means of a third PMOS transistor 33 to which an output pulse of the address variation detector is applied to a gate; load means of fourth and fifth transistors 34 and 35 connected in parallel with each of the charging means; And a pair of bit lines (BL, BL) and a plurality of memory cells (14) connected to the bit lines to charge and equalize the bit lines during read and write operations. Adjusting means, the gate voltage adjusting means being a write enable signal;

An inverting means (11) for inverting and outputting the input signal, a buffer means (12) for buffering the write enable signal, and a first gate connected to the inverting means (11) and a drain connected to a power supply voltage. A power supply voltage is connected to the NMOS transistor 21 and the buffer means 12 and is connected between the source of the first NMOS transistor 21 and the ground, and the second NMOS transistor 22 is applied. And a pulse generating means (20) consisting of a third NMOS transistor (23) connected in parallel with each other).

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