KR900702465A - Repeat phenomenon eliminator - Google Patents

Abstract

No content

Description

Repeat phenomenon eliminator

Since this is an open matter, no full text was included.

3 is a block diagram of a select and erase controller in accordance with the principles of the present invention, FIG. 4 is a block diagram of a single fundamental frequency cancellation processor in accordance with the principles of the present invention, and FIG. 5 is a block diagram of a multiple basic frequency cancellation processor in accordance with the principles of the present invention. leadership.

Claims (13)

And a developing input means for providing a developing signal indicative of a residual phenomenon to be erased, a timing input means for providing a timing signal indicative of a repetition rate of the developing phenomenon, and an inputting portion for the developing signal and the timing signal, to actually remove the developing phenomenon. Processor means for generating a cancellation signal, an output means connected to said processor means for providing an erasing phenomenon as a function of said cancellation signal, located in said processor means, and filtering as a function of said developing signal and a timing signal; Adaptive filter means for generating the cancellation signal by adapting the means filtering characteristic, and phase means for maintaining the adaptation of the filtering characteristic within a 90 degree phase of the developing signal, the adaptive filter means being located in the processor means. Iteration elimination controller. 2. The apparatus according to claim 1, wherein the adaptive filter means receives sine and cosine means for generating sine and cosine of the timing signal, respectively, so that the frequency is canceled, and the sine and cosine signals, respectively, First and second filter means for providing first and second erase signals, respectively, as a function of first and second filter weights of second filtering means, and providing the cancellation signal by combining the first and second erase signals. Adding means, and first and second adapter means for adapting the first and second filter weights as a function of the sine and cosine signals and the developing signal, wherein the phase means comprises: the first and second means; And the adapter means adjusts the phases of the sine and cosine signals provided to the first and second adapter means so as to be within a 90 degree phase of the developing signal. 3. The repetitive phenomenon cancellation according to claim 2, wherein the interphase means includes means for measuring a delay between the provision of the erase signal and acceptance of the development signal and means for adjusting the phase as a function of the measured delay. Controller. 4. The repetitive phenomenon canceling according to claim 3, wherein said phase means includes means for measuring a processing delay of said processing means, and said adjusting means also adjusts said phase as a function of processing delay of said processor means. Controller. 3. The apparatus of claim 2, wherein said phase means includes: test signal means for generating a test signal provided to said output means, third filter means for receiving said test signal and providing a filtered signal as a function of a third filter weight; Difference means for providing a difference signal between the filtered signal and the developing signal, delay means for providing a delayed test signal from the test signal, and weighting the third filter as a function of the delayed test signal and the difference signal; And a third adapter means for adapting. 2. The repetition of claim 1, wherein said phase means includes means for measuring a delay between the provision of said cancel signal and acceptance of said developing signal and adjusting means for adjusting said phase as a function of the measured delay. Phenomenon elimination controller. 7. The repetitive phenomenon canceling according to claim 6, wherein said phase means includes means for measuring a processing delay of said processing means, and said adjusting means also adjusts said phase as a function of processing delay of said processor means. Controller. 2. The apparatus of claim 1, wherein said phase means comprises: test signal means for generating a test signal provided to said output means, third filter means for receiving said test signal and providing a filtered signal as a function of a third filter weight; Difference means for providing a difference signal between the filtered signal and the developing signal, delay means for providing a delayed test signal from the test signal, and weighting the third filter weight as a function of the delayed test signal and the difference signal. And a third adapter means for adapting. 2. The repetition cancellation controller according to claim 1, wherein said phase means comprises means for setting a predetermined phase value. 2. The repetition phenomenon eliminating controller according to claim 1, wherein said timing input means includes timing means for detecting said repetition rate of said phenomenon and generating said timing signal. 11. The repetition phenomenon elimination controller according to claim 10, comprising a tachometer of said timing means. 11. The repetition cancellation controller according to claim 10, wherein said timing means includes a phase locked loop circuit. 11. The repetition cancellation controller according to claim 10, wherein said timing input means includes a function generator for generating said timing signal. ※ Note: The disclosure is based on the initial application.