KR900016096U - Shared input / output port circuit for communication between CPUs - Google Patents

Shared input / output port circuit for communication between CPUs

Info

Publication number
KR900016096U
KR900016096U KR2019890002029U KR890002029U KR900016096U KR 900016096 U KR900016096 U KR 900016096U KR 2019890002029 U KR2019890002029 U KR 2019890002029U KR 890002029 U KR890002029 U KR 890002029U KR 900016096 U KR900016096 U KR 900016096U
Authority
KR
South Korea
Prior art keywords
cpus
communication
output port
port circuit
shared input
Prior art date
Application number
KR2019890002029U
Other languages
Korean (ko)
Other versions
KR910005479Y1 (en
Inventor
김명규
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019890002029U priority Critical patent/KR910005479Y1/en
Publication of KR900016096U publication Critical patent/KR900016096U/en
Application granted granted Critical
Publication of KR910005479Y1 publication Critical patent/KR910005479Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
KR2019890002029U 1989-02-27 1989-02-27 I/o port sharing circuit for communication between cpus KR910005479Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019890002029U KR910005479Y1 (en) 1989-02-27 1989-02-27 I/o port sharing circuit for communication between cpus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019890002029U KR910005479Y1 (en) 1989-02-27 1989-02-27 I/o port sharing circuit for communication between cpus

Publications (2)

Publication Number Publication Date
KR900016096U true KR900016096U (en) 1990-09-03
KR910005479Y1 KR910005479Y1 (en) 1991-07-27

Family

ID=19283974

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019890002029U KR910005479Y1 (en) 1989-02-27 1989-02-27 I/o port sharing circuit for communication between cpus

Country Status (1)

Country Link
KR (1) KR910005479Y1 (en)

Also Published As

Publication number Publication date
KR910005479Y1 (en) 1991-07-27

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