KR900011149U - DBM circuit for wired TV tuner - Google Patents

DBM circuit for wired TV tuner

Info

Publication number
KR900011149U
KR900011149U KR2019880019287U KR880019287U KR900011149U KR 900011149 U KR900011149 U KR 900011149U KR 2019880019287 U KR2019880019287 U KR 2019880019287U KR 880019287 U KR880019287 U KR 880019287U KR 900011149 U KR900011149 U KR 900011149U
Authority
KR
South Korea
Prior art keywords
tuner
wired
dbm circuit
dbm
circuit
Prior art date
Application number
KR2019880019287U
Other languages
Korean (ko)
Other versions
KR940007016Y1 (en
Inventor
최상구
Original Assignee
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사 filed Critical 삼성전자 주식회사
Priority to KR2019880019287U priority Critical patent/KR940007016Y1/en
Publication of KR900011149U publication Critical patent/KR900011149U/en
Application granted granted Critical
Publication of KR940007016Y1 publication Critical patent/KR940007016Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/10—Adaptations for transmission by electrical cable
    • H04N7/102—Circuits therefor, e.g. noise reducers, equalisers, amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Superheterodyne Receivers (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Transmitters (AREA)
KR2019880019287U 1988-11-29 1988-11-29 Double balanced mixer circuit of catv KR940007016Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019880019287U KR940007016Y1 (en) 1988-11-29 1988-11-29 Double balanced mixer circuit of catv

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019880019287U KR940007016Y1 (en) 1988-11-29 1988-11-29 Double balanced mixer circuit of catv

Publications (2)

Publication Number Publication Date
KR900011149U true KR900011149U (en) 1990-06-04
KR940007016Y1 KR940007016Y1 (en) 1994-10-07

Family

ID=19281656

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019880019287U KR940007016Y1 (en) 1988-11-29 1988-11-29 Double balanced mixer circuit of catv

Country Status (1)

Country Link
KR (1) KR940007016Y1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102538326B1 (en) 2023-02-27 2023-05-31 주식회사 시원조경 Prefabricated decorative boat

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102538326B1 (en) 2023-02-27 2023-05-31 주식회사 시원조경 Prefabricated decorative boat

Also Published As

Publication number Publication date
KR940007016Y1 (en) 1994-10-07

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Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20011004

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee