KR900007377Y1 - Satellitic broad casting receiver using phase locked loop synthesized frequency - Google Patents

Abstract

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Description

Phase Locked Loop Frequency Synthesis Satellite Receiver

1 is a basic system diagram of a satellite broadcasting receiver.

2 (a) and (b) are channel distribution diagrams of satellite broadcasting.

3 is a phase locked loop frequency synthesized satellite broadcasting receiver according to the present invention.

4 is an external view of a channel control panel according to the present invention.

5 is an operational waveform diagram of FIG.

* Explanation of symbols for main parts of the drawings

1: low noise amplifier 2: local oscillator

3: first mixer 4: first intermediate frequency filter and amplifier

5: second mixer 6: second intermediate frequency filter and amplifier

7 demodulator 8 voltage controlled oscillator

9: frequency divider 10: program divider

11: reference oscillator 12: phase comparator

13: low pass 14: control key

15 memory 16 central processing unit

17: channel display device 18: data register

The present invention relates to a Phase Looked Loop (Frequency Synthesized) receiver used to select a satellite television broadcast receiver channel. In particular, one channel is fine-tuned to automatically adjust all other channels. The present invention relates to a phase locked loop frequency synthesized satellite radio receiver that can be used.

In general, in order to receive a broadcast via satellite, it is necessary to have a basic system as shown in FIG.

That is, the signal received by the parabola antenna 10 as shown in Figure 1 is 3. 7GHZ-4. A weak signal in the 2 GHZ band, which is amplified with a constant gain without conversion of the frequency through the low noise amplifier 20, and then converted into an intermediate frequency in the frequency converter 30, and then in a television frequency band in the receiving device 40. The second frequency conversion is applied to a television set installed indoors.

3. 7GHZ-4 received by the parabola antenna 10. The satellite broadcasting television signal in the 2 GHZ band is composed of 24 channels (24CH) in the 500 MHz band as shown in the satellite radio broadcasting channel distribution diagrams of Figs. 2 (a) and (b). It consists of horizontal polarization and the order of vertical and horizontal polarization can be changed.

3. 7GHZ-4. After converting the entire 500MHZ band in 2 GHZ to the first intermediate frequency (mainly 950MHz-1450MHz), the second intermediate frequency (mainly 70MHZ) by selecting one channel using the channel selection circuit at the converted first intermediate frequency There is a method of converting and demodulating the.

The frequency conversion circuit used in the above-described conversion method is a typical example of operating a frequency synthesizer using a phase-locked loop. The channel synthesis circuit of the frequency synthesis reception method using the phase lookup loop as described above stores each channel selection data for 24 channels in a microprocessor memory and stores a local oscillation frequency according to the channel selection data. The oscillation of the phase locked loop PLL is selected to select a channel. The conventional channel selection circuit using the phase locked loop as described above reads the selected data of the corresponding channel from the internal memory when the channel is selected by the key selection, and oscillates the phase locked loop (PLL) through the data register. Output as control data. At this time, the phase locked loop PLL generates a local oscillation frequency corresponding to each channel selection data input as described above, and inputs it to a mixer to select a desired channel signal.

However, the channel selection circuit of the phase locked loop (PLL) frequency synthesizing method has all the channels as long as the local oscillation frequency deviates when the frequency of the local oscillator in the frequency converter 30 installed outdoors is slightly different from the reference frequency. The choice of deviates and this has left the user unable to adjust channel selection.

Accordingly, an object of the present invention is to provide a frequency synthesized receiver capable of automatically correcting a frequency deviation of all channels by finely adjusting one channel when the local oscillator frequency is out of a reference frequency.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram according to the present invention, which is received by the antenna 3. 7GHZ-4. A low noise amplifier (1) for amplifying weak signals of 2 GHZ with constant gain without change in frequency, a local oscillator (2) for oscillating output of a constant first local oscillation frequency, and amplified output from the low noise amplifier (1) A first mixer 3 for mixing a signal and a local oscillation frequency of the local oscillator 2 to output a mixed (differential frequency) signal, and a mixed (differential frequency) signal outputted from the mixer 3. A first intermediate frequency filter and an amplifier 4 for inputting and filtering and amplifying only the first intermediate frequency band, and corresponding to the first intermediate frequency signal and the selection channel output from the first intermediate frequency filter and the amplifier 4. A second mixer 5 for mixing a second local oscillation frequency and outputting a mixed frequency (differential frequency) signal, and a second intermediate for amplifying and outputting a second intermediate frequency output from the second mixer 5. Frequency filter and increase And a demodulator 7 for inputting and demodulating the signal output from the second intermediate frequency filter and the amplifier 6 and outputting the signal to the TV, and oscillating a predetermined frequency according to the input oscillation control voltage. A voltage controlled oscillator 8 outputting at the second local oscillation frequency of the second mixer 5 and a frequency divider 9 for dividing the second local oscillation frequency output from the voltage controlled oscillator 8 at a predetermined frequency. ), A program divider 10 for dividing and outputting a signal divided by the frequency divider 9 at a division ratio corresponding to a predetermined data input value, and a reference oscillator 11 for oscillating and outputting a predetermined reference frequency. And a phase comparator 12 for inputting a frequency signal output from the reference oscillator 11 and a frequency signal output divided by the program divider 10 to compare phases of two frequencies and generating the phase difference signal. , A low pass filter 13 for low-pass filtering the phase difference signal output from the phase comparator 12 and outputting the oscillation control voltage of the voltage controlled oscillator 8, and a user connected to the exterior of the receiver Control key 14 for outputting manufacturing information (corresponding key signal) when the channel up / down selection key, channel fine adjustment key, volume adjustment key and the like are executed, and fine adjustment data for one channel by predetermined control. Memory 15 for outputting memory data, control information output from the control key 14, input corresponding channel data in the internal memory, and data of the memory 15 to input selected channel data; A central processing unit (CPU) 16 for outputting channel selection data; a display device 17 for inputting display data output from the CPU 16 to display a current selection channel; and Of CPU (8) It consists of a data register 18 for inputting output adjustment data and outputting it to a programmable divider 15.

3. 7GHZ-4 in which the local oscillator 2, the first mixer 3, the first intermediate frequency filter and the amplifier 4 are received. Corresponding to the first frequency converter 120 for converting and amplifying and outputting a signal of 2 GHZ into a frequency of the 950MHZ-1450MHZ band, it is installed outdoors. And the second mixer 5, the second frequency filter, the amplifier 6, and the demodulator 7 of the channel band desired for the signal of the first intermediate frequency 950MHZ-1450MHZ outputted from the first frequency converter. The second frequency conversion demodulator 130 converts the signal into a signal and demodulates the output signal.

Corresponding to the phase locked loop (PLL) 140, the control key 14, the memory 15, the CPU 16, and the channel indicator 17 correspond to the fine adjustment section.

4 is an external view of the channel control panel according to the present invention, and the channel control panel according to the present invention has a control key 14 and a channel display device 17 of FIG.

The channel display device 17 has two drivers for displaying 24 channels and a driver capable of driving the seven segments by decoding display data.

The control key 14 is composed of a channel selection key 121, a fine adjustment function key 122, a fine adjustment terminal key 123, and a fine adjustment LED 24. At this time, the channel selection key 121 and the fine adjustment function key 122 is configured as an up / down key (↑ / ↓) to output a channel signal to be up or down.

5 is an operation flowchart of the central processing unit 16 of FIG. 3 according to the present invention.

Hereinafter, an operation example of FIG. 3 according to the present invention will be described with reference to the accompanying drawings.

When the satellite broadcasting television signal fR (3. 7GHZ-4.2 GHZ), now propagated from the satellite via the antenna ANT, the low noise amplifier 1 amplifies low noise as described above and the first mixer 3 ).

At this time, the first mixer 3 mixes and mixes the signals of the first local oscillation frequency (Lo1) oscillated from the local oscillator 2 and the received satellite broadcasting television signal (3.7GHZ-4.2GHZ). A frequency (differential frequency) fR ± Lo1 (950GHZ-1450GHZ) is output to the first intermediate frequency filter and the amplifier 4. The first intermediate frequency filter and the amplifier 4 which input the signal of the mixing frequency (differential frequency) (fR ± Lo1) 950GHZ-1450GHZ output from the first mixer 3 are the image frequency included in the frequency ( After removing a noise such as an image frequency, a predetermined amplification is performed to input only the first intermediate frequency f ₁ f ₁ (950GHZ-1450GHZ) to the second mixer 5.

In the above state, the key of the channel up key UP (↑) or the down key ↓ of the channel selector 121 in the control key 14 of FIG. 4 is pressed and the key signal is input to the CPU 16. do. At this time, the CPU 16 recognizes the channel up / down key signal by scanning the control key 14 at a predetermined period.

The CPU 16 that recognizes the pressing of the channel select key 121 by the scan operation as described above up and down the current channel while the channel up / down key signal is input.

For example, if the channel down key ↓ is pressed while the current channel data in the CPU 16 is channel 14, the channel 14 is down to channel 13, and the channel down key ↓ is When off, the channel down operation is stopped.

The CPU 16 reads the corresponding channel selection data stored in the internal memory area (ROM area or RAM area) in the process of FIG. 5A, and outputs a read control signal to the memory 15 to perform fine adjustment data. Lead. The CPU 16 having read the channel selection data and the fine adjustment data as described above outputs the display data of the selected channel to the channel display device 17 to display the selected channel state.

When the first product comes out, the fine tuning data " 0 " (Zero) stored in the memory 15 is the limit value of the fine tuning data stored in the memory 15 is a data value of ± 10KHZ.

The CPU 16 inputting the fine adjustment data and the channel selection data as described above outputs the data value to which the channel selection data and the fine adjustment data are added to the data register 18 in FIG. 5 (b). In step 3), it is searched whether the fine adjustment enable key 123 is pressed. At this time, the data register 18 is composed of a latch composed of a D-type flip-flop to latch the data output from the CPU 16 and apply the divided data of the programmable counter 10. The programmable divider 10 divides the frequency signal output from the frequency divider 9 into a division ratio corresponding to the data value output from the data register 18 and outputs it to the phase comparator 12.

The phase comparator 12 for inputting the signal divided and output from the program divider 10 compares a phase of the reference frequency signal oscillated from the reference oscillator 11 with the phase of the divided input frequency and phase difference between the two signals. Generates an error voltage EV corresponding to.

The error voltage EV output from the phase comparator 16 is low-pass filtered by the low pass filter 13 to remove noise, and is then supplied to the voltage controlled oscillator 8 as an oscillation control voltage.

The voltage controlled oscillator 8, which inputs the error voltage EV filtered out from the low pass 13, oscillates a second local oscillation frequency Lo2 corresponding to the error voltage EV to generate a second mixer. (5) and frequency divider (9). At this time, the second mixer 5 inputting the second local oscillation frequency Lo2 output from the voltage controlled oscillator 8 is a first intermediate filter amplified output from the first intermediate frequency filter and the amplifier 4 described above. A frequency f ₁ F ₁ (about 950GHZ-1450GHZ) and the second local oscillation frequency Lo2 are mixed to input a mixing frequency f ₁ F ₁ ± Lo2 to the second intermediate frequency filter and amplifier 6. .

The second intermediate frequency filter and the amplifier 6 output the second intermediate frequency f ₁ F ₂ to the demodulator 7 by performing intermediate frequency filtering on the input mixed frequency f ₁ F ₁ ± Lo ₂ .

Therefore, if the second local oscillation frequency Lo2 outputted from the voltage controlled oscillator 8 is a frequency of (1020GHZ-1520GHZ), the mixing frequency f ₁ F ₂ output from the second mixer 5 is about 70MHZ. .

The demodulator 7 which inputs the second intermediate frequency f ₁ F ₂ output from the second intermediate frequency filter and the amplifier 6 demodulates the input signal into a television signal and inputs it to the TV. At this time, the TV reproduces and displays the television signal output from the demodulator 7.

However, when the first local oscillation frequency Lo1 output from the local oscillator 2 deviates from the reference frequency when the channel is selected by the above operation, the first local oscillation frequency Lo1 is equal to the error of the first local oscillation frequency Lo1. The mixing frequency fR ± Lo1, which is the output of the mixer 1, is also changed. Accordingly, as the first local oscillation frequency Lo1 is out of frequency, the frequencies of all channels are out of range. Therefore, when the first local oscillation frequency Lo1 oscillated by the local oscillator 2 changes, accurate tuning becomes difficult, and thus a lot of noise is included in the screen reproduced on the TV.

When the user who views the screen containing noise presses the fine adjustment terminal key 123 (see FIG. 4) in the control key 14 because the screen is unsatisfactory, the fine adjustment signal is output from the control key 14.

The CPU 16 inputting the fine adjustment signal output from the control key 14 determines that the screen is not satisfied in FIG. 5 (C).

That is, it is determined that the fine adjustment terminal key 123 has been pressed, and the fine adjustment LED 124 in the control key 14 is driven and turned on in the process of FIG. 5 (d).

As described above, when the user presses the Up / Down (↑ / ↓) key of the fine adjustment function key 122 in the control key 14 while the fine adjustment LED 124 is turned on, the fine adjustment up / down is performed. Down data is input to the CPU 16.

At this time, the CPU 16 outputs the fine adjustment data input in the process of FIG. 5 (e) to the data register 18.

The data register 18 latches the fine adjustment data output from the CPU 18 and outputs the divided data of the program divider 10. The program divider 10 divides the output of the frequency divider 9 for outputting a predetermined division frequency of the second local oscillation frequency Lo2 by the divided data value of the data register 18 to perform a phase comparator 12. To enter.

For example, if the output is A (A is frequency) when the first division value input to the program divider 10 (the output of the register register 10 is “1000”), the output of the data register 18 is When up / down (eg, from 1000 to 1001 → 1001 state or from 1000 to 0111 → 0110), the output A of the program divider 10 is increased or decreased. Therefore, the program divider 10 divides the output of the frequency divider 9 programmatically under control and inputs it to the phase comparator 12.

The phase comparator 12 compares the phase of the reference frequency signal oscillated from the reference oscillator 11 and the frequency output from the program divider 10 to obtain an error voltage EV corresponding to the phase difference. 13), and the low pass filter 13 outputs the filtered error voltage EV as the oscillation control voltage of the voltage controlled oscillator 8.

Therefore, the output of the phase comparator 12 increases or decreases according to the change of the output of the program divider 10 so that the output of the voltage controlled oscillator 8 which inputs the output of the phase comparator 12 as a control signal also changes. do.

For example, when the up key ↑ of the fine adjustment function key 122 is pressed, the output of the program divider 10 is increased to increase the error voltage EV output of the phase comparator 12, and at this time, the voltage controlled oscillator 8 The second local oscillation frequency Lo2, which is oscillated from N, is also increased. On the contrary, when the down key ↓ of the fine adjustment key 122 is pressed, the second local oscillation frequency Lo2 is decreased.

When the second local oscillation frequency Lo2 of the voltage controlled oscillator 8 is changed, the mixing range of the second mixer 5 is changed to fine tune the channel selection.

Meanwhile, in the process of FIG. 5 (E), the CPU 18 which outputs fine adjustment data according to the pressing of the fine adjustment function key 122 is continuously operated by the fine adjustment terminal key 123 in FIG. 5 (F). Search if it is pressed. If the fine-adjustable terminal key 123 is not pressed in the process of FIG. 5, the screen is judged to be unsatisfactory and jumps to the above-described process of FIG. 5 (e) to adjust the fine adjustment function key 122. Continue to print fine adjustment data as you press.

Therefore, it can be seen that the fine tuning data changes while the fine tuning function key 122 of FIG. 4 is pressed, thereby changing the second local oscillation frequency Lo2 of the voltage controlled oscillator 8. By performing the fine adjustment as described above, when the state of the TV screen connected to the demodulator 7 is in the best state, when the user finishes the fine adjustment and the user presses the fine adjustment terminal key 123 again, the CPU 16 returns to the fifth. In step (bar) it is determined that the fine adjustment terminal key 123 is pressed.

That is, when the screen is determined to be satisfactory, the CPU 16 turns off the fine adjustment LED 124 and continues the output of the fine adjustable data output to the data register 18 while simultaneously adjusting the finely adjusted data to the memory 15. Load (Save) At this time, the memory 15 inputting the fine adjustment data is an EEPROM (Electric Erasble Programmable ROM), which is a nonvolatile memory, so that the fine adjustment data is stored even without power. The fine tuning data loaded and stored in the memory 15 can be equally used in other channels, and fine tuning of one channel can compensate for the frequency error of the local oscillator 2. That is, by adjusting 20 MHZ for each channel interval transmitted from the satellite, fine adjustment of one channel is possible to adjust the remaining channels. That is, when the first local oscillation frequency Lo1 outputted from the local oscillator 2 oscillates several tens of mechahels from the reference frequency and an error occurs, the first intermediate frequency band fR ± Lo1 is transmitted from the first mixer 3. All channel frequencies within (950GHZ-1450GHZ) (500MHZ band) are also changed in the same way. At this time, when the second local oscillation frequency Lo2 of the voltage controlled oscillator 8 is changed as the fine adjustment data by the adjustment of the fine adjustment function key 122 in the control key 14 to compensate the error for one channel. In addition, since the remaining 23 channel frequencies are changed in the same manner, the fine tuning data can be adjusted.

Therefore, in the present invention, the fine tuning data is stored in the nonvolatile memory and the channel is tuned by the channel selection data and the stored fine tuning data whenever the channel is selected, thereby automatically compensating for the error of the remaining channels by one channel fine tuning.

In addition, since the memory 15 retains data even when the power is turned off, fine adjustment is not required even when the power supply is turned off, and the memory 15 can be electrically changed. If the oscillation frequency is changed again, the readjustment is possible.

Therefore, as described above, the present invention obtains the effect of making fine adjustments for one channel by making fine adjustments to one channel, thereby compensating for the frequency deviation of local oscillators in a block down converter installed outdoors. In addition, it is possible to take advantage of the stability of the frequency selection of the frequency synthesis receiver has the advantage that can always receive the broadcast in the optimal state.

Claims (1)

Low noise amplifier 1 for low noise amplifying and outputting the inputted satellite broadcast signal, and having a first local oscillator 2 therein, the output of the low noise amplifier 1 and the output of the first local oscillator 2 Mixes the first frequency converter 120 for outputting a first intermediate frequency, and outputs a second intermediate frequency by mixing the output first intermediate frequency and an input second local oscillation frequency, and outputting the second intermediate frequency. The second frequency conversion demodulator 130 oscillates a second local oscillation frequency with an error voltage EV obtained by comparing a phase of a reference frequency and a comparison frequency with a second frequency conversion demodulator 130 for demodulating and outputting a frequency. In a phase locked loop composite satellite broadcast receiver having a phase locked loop (140) inputted to a frequency band, the frequency for dividing and outputting the second local oscillation frequency connected to the phase locked loop (140) is output. The frequency division signal 9 is connected to an output terminal of the frequency divider 9 and divided into a frequency division ratio corresponding to an input value of predetermined data by dividing the divided signal outputted as a comparison signal of the phase locked loop 140. It has a program divider 9, a channel selection key 121, a fine adjustment function key 122, a fine adjustment terminal key 123, and a fine adjustment LED 24, and channel selection by pressing each key. A control key 14 for outputting data, fine-tuning data and fine-tuning signals and displaying the fine-tuning state by input display data, and a nonvolatile memory for recording, reading, and outputting fine-tuning data under predetermined control ( 15), and an output terminal is connected to the divided data input terminal of the program divider 10, and the input channel selection data is provided as the divided data of the program divider 10 to provide the phase locked loop. A data register 18 for causing a second local oscillation frequency of 140 to be varied; and a control key 14, a nonvolatile memory 15, and a data register 18 connected from the control key 14 The stored data of the nonvolatile memory 15 is read by the output channel selection data input, and the signal of the sum of the fine adjustment data and the selection channel data is output as the channel selection data to the data register 18, and the control key A central processing unit 16 for changing the channel selection data output to the data register 18 at the time of outputting the fine adjustment signal and the fine adjustment data from the 14 and recording the fine adjustment data in the nonvolatile memory 15; A phase locked loop composite satellite broadcast receiver characterized in that the configuration.