KR900007358Y1 - Circuit for synchronizing clock signal between two processors - Google Patents

Abstract

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Description

Two Processor Clock Signal Synchronization Circuit

1 is a diagram illustrating two processor clock signal synchronization circuits of the present invention.

* Explanation of symbols for main parts of the drawings

A: Power Supply B: Master Flow Processor

C) slave processor d) address bus control circuit

E: memory bar: 2-way bus control circuit

4: High speed switching circuit R1, R2: Resistance

D1: Diode TR1: Transistor

CLK: Clock Terminal CTL: Control Terminal

Add-Bus1 to Add-Bus3: Address Bus

Data-Bus1 to Data-Bus3: Data Bus

The present invention relates to two processor clock signal synchronizing circuits in a computer, and more particularly, to two processor clock synchronizing circuits which can be synchronized by supplying an accurate clock signal between processors by adding a fast switching circuit at two processor times.

In general, the synchronization of a computer means that when two processors use the same storage device in order to use the same storage device, the other processor cannot use the storage device. For the synchronization as described above, oscillation circuits of the same frequency should be used in the processor or oscillation circuits of different frequencies should be used, and separate signal lines should be used for intercommunication for synchronization. Due to the value of the oscillation frequency time, different circuits in the inside operate at different times, causing the processor to malfunction.

In order to solve the above problems, the present invention provides one of two processors as the master processor and the other as the slave processor to supply the correct clock signal to the slave processor so that it can be controlled by the slave processor. By connecting the circuit to be synchronized, the present invention will be described in detail by the accompanying drawings as follows.

Connect the power supply (A) and the power generator (x1) that supply power to each circuit to the master processor (B), and the control terminal (CTL) of the master processor (B) is the address bus control circuit (D) and the bidirectional bus circuit. (B), the address bus terminal (Address Bus1) of the master processor (I) is connected to the address bus control circuit (D), and the data terminal DATA of the master processor (B) is a data bus. It is connected to the bidirectional bus control circuit (bar) through the terminal DATA-Bus1, and the address terminal Add3 of the slave processor (C) is connected to the address control circuit (D) through the address bus terminal (Address Bus2). In addition, the data terminal DATA of the slave processor C is connected to the bidirectional bus control circuit F through the data bus terminal DATA Bus2, and the address bus control circuit D is connected to the address bus terminal Add- Via Bus3) In the two processor clock synchronization circuits connected to the memory (e) and the memory (e) are connected to the bidirectional bus control circuit (bar) through the data bus terminal (Data-Bus3), the clock of the master processor (I) The high speed switching circuit (g) consisting of resistors R1, R2, reverse diode D1, and transistor TR1 is connected to the clock terminal CLK of the terminal CLK and the slave processor C. Referring to the effect of the present invention configured as follows.

First, when the driving power is supplied from the power supply unit to each circuit, the main system (not shown) frequency is supplied to the master processor (I), and the master processor (B) is continuously operated by the frequency in the main system. do.

This system frequency remains constant as long as power is applied.

Subsequently, when the master processor (I) uses the memory (L), the master processor (B) does not output the frequency (ie clock frequency) used for the slave processor (C) through its clock signal terminal (CLK). Since the high speed switching (g) does not operate, the slave processor (c) stops operating.

Therefore, the master processor (b) applies control signals to the address bus control circuit (D) and the bidirectional bus control circuit (B) through its control terminal (CTL), and the address bus (Add-Bus2) of the slave processor (C). The data bus Data-Bus2 is disconnected from the memory (e), while in the master processor I, the address bus control circuit D and the address bus Add-Bus1 and the data bus Data-Bus1 are connected to each other. An address signal (Add-Bus3) is applied to the memory (e) by applying an address signal and a data signal to the bidirectional bus control circuit (bar), respectively, and the memory (e) via the data bus (Data to Bus3). You will exchange data with.

On the other hand, when the slave processor (C) operates, the master processor (B) applies the clock frequency through its clock terminal CLX to the base terminal of the transistor TR1 through the resistor R1 in the high speed switching circuit. When the transistor TR1 is turned on and the slave processor C is driven, the address bus control circuit D and the bidirectional bus control circuit B are operated through the address bus Add-Bus3 and the data bus Data-Bus2. ), So that the address bus (Add-Bus1) and data bus (Data-Bus1) of the master processor (I) and the data bus (Data-Bus1) are blocked from the memory (e), while the address bus (Add-Bus2) of the slave processor (C) An address signal and a data signal are applied to the address bus control circuit (D) and the bidirectional bus control circuit (B) through the data buses Data to Bus2, respectively, and addressed to the memory A through the address bus Add-Bus3. It dropped calls and also via the data bus (Data-Bus3)

You will exchange data with the memory (e).

The resistors R1 and R2 are for controlling the driving voltage of the transistor TR1, and the diode D1 is for fast operation of the transistor TR1.

As described above, the present invention provides a fast and accurate clock signal to the slave processor by connecting a high speed switching circuit that supplies the clock signal accurately and quickly between the master processor and the slave processor in order to synchronize the two processors. There is an effect that can simplify the circuit without using a separate signal line for synchronization.

Claims (1)

Two devices that can be synchronized with the power supply (A), the master processor (B) and slave processor (C), the address bus control circuit (C), the memory (E), and the bidirectional bus control circuit (B). In the processor clock signal synchronizing circuit, a high speed switching circuit comprising a resistor R1, R2, diode D1, and transistor TR1 is provided at the clock terminal CLK of the master processor (I) and the slave processor (C). Two processor clock signal synchronization circuits, each of which is configured to supply an accurate and fast clock signal to a slave processor by connecting a circuit.