KR900006471B1 - Debugging system of teletext - Google Patents

Abstract

The debug system is for testing the memory or microprocessor wiht RS- 23C port in failure state. The debugging program of the TTX decoder stored in a ROM (28) is loaded on a RAM (29) after turning on the power. A microprocessor (27) processes the program and provides the result to a second data buffer (34) sending the serial data to an user terminal (300) through the RS-232C. After selecting the mode by the user, the second data buffer provides the parallel input data to the processor. There are test modes for testing a colour video display generator, a RAM, a digital teletext processor, and a teletext data format in prefix processor.

Description

Debugging System for Teletext Decoder

1 is a conceptual diagram according to the present invention.

2 is a circuit diagram according to the present invention.

3 is a flow chart according to the present invention.

(3a) Main flow chart

(3b) subflow chart

* Explanation of symbols for main parts of the drawings

21 cable 22 first buffer

23: second buffer 24: address decoder

25: dip switch 26: switch

27: processor 28: ROM

29: RAM 30: Oscillation and Dispensing Circuit

31: Baurate selection unit 32: Divider

33: clock generator 34: second data buffer

35: selection and control 36: transmitter

37: receiver 100: TTX decoder

200: debug system 300: terminal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a teletext decoder (Decoder), and in particular, a debug system for a teletext decoder (DEBUG) that can test the coordination and failure of the teletext decoder (hereinafter referred to as "TTX"). It is about.

In order for a TV viewer to watch a text multicast (TTX), a TTX dedicated receiver (hereinafter referred to as a "TTX decoder"), which is designed to meet the text multicast signal standard transmitted from a broadcasting station, is required. The TTX dedicated receiver may be embedded in a TV or made into a separate adapter format.

Since the TTX decoder can be distributed in large quantities unlike an editing or data transmission device, a price problem should be considered, and on the other hand, the TTX decoder should have various functions in terms of service, and thus should provide convenience to users.

In order to satisfy the above-mentioned double-sided property, a country that implements foreign character multiplexing broadcasting is developing and using a dedicated integrated circuit (IC).

The domestic industry continues to conduct research experiments on the TTX decoder in preparation for the future implementation of multi-text broadcasting.

However, most of the text multicast screens in Korea should be composed of Korean characters. Therefore, the issue of Hangul processing is considered carefully. In KBS, the character multicasting system of each country was examined. As a result, North American NABTS (North American Broadcast teletext standard) method was used. This method, which has various functions and is easy to accept Hangul, is continuously researched and reviewed. Even if the TTX decoder was developed using the NABTS method, first, a device that can test whether the TTX decoder meets the character broadcasting use or specification is required. Even if it is distributed to the user, if a failure of the TTX decoder occurs, there is a need for a device that can test the TTX decoder as well as technically about this.

Accordingly, an object of the present invention is to provide a system that can easily test the abnormality of the memory and other processors using the debug system when the TTX decoder using the microprocessor occurs.

Another object of the present invention is to provide a system that can directly communicate with the user by connecting the input and output port of the RS-232C connection method with the terminal to give the convenience of the test.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram of the debugging of the TTX decoder according to the present invention, and installs the debug system 200 of the TTX decoder 100 of the present invention between the TTX decoder 100 which is a TTX dedicated receiver and the user's terminal 300. Thus, the user can test RAM (RAM), CRTC (CRT controller), and DTP (Digita1 Teletext Procesor) debug and state used in the TTX decoder 100.

의 제어신호를 발생하는 어드레스 디코더(24)와, 사용자에 의해 조작되는 것으로 터미널과 데이타 전송에 필요한 보우레이트(전송속도 : 9600bps, 4800bps, 120-bps, 300bps)를 선택할 수 있는 스위치(26)와, 상기 제어버스(P0-Pn)와 연결되어 디버그 시스템(200)의 구동에 필요한 기본 클럭을 제공하는 발진 및 분주회로(30)와, 상기 발진 및 분주회로(30) 및 스위치(26)간에 상기 제어버스(P0-Pn)와 연결되어 상기 스위치(26)의 선택에 따라 상기 발진 및 분주회로(30)에서 출력하는 발진주파수의 선택으로 전송속도를 선택하는 보우레이터 선택부(31)와, 상기 제어버스(P0-Pn)와 연결되어 제어버스(P0-Pn)를 통해 입력되는 신호로 부터 상기 보우레이터 선택부(31)에서 선택되는 전송속도에 맞는 보우레이트 주파수를 소정으로 분배하는 분주기(32)와, 상기 제1버퍼(23), 프로세서(27), 롬(28) 및 램(29)의 데이타버스(D0-D7)와 연결되어 사용자 측의 입출력 데이타를 선택 및 제어부(35)의 제어에 따라 버퍼링하는 제2데이다 버퍼(34)와, 상기 제2데이타버퍼(34)와 연결되어 출력되는 병렬데이타를 직렬로 변환하여 RS-232C 연결방식의 라인을 통해 사용자측 터미널(300)측으로 전송하는 송신기(36)와, 상기 사용자측 터미널(300)의 RS-232C 연결방식라인을 통해 입력된 직렬데이타를 병렬데이타로 변환하여 디버그 시스템(200)의 제2데이타버퍼(34)에 입력하는 수신기(37)와, 상기 분주기(32)에서 분주된 클럭신호를 받아 상기 제2데이타 버퍼(34)에서 요구되는 데이타의 직렬전송 및 수신데이타의 속도와 동기시키기 위한 클럭을 발생하는 클럭발생부(33)로 구성된다.FIG. 2 is a detailed circuit diagram of the debug system 200 of FIG. 1 according to the present invention. A 40-pin cable is connected to a host processor of the TTX decoder 100 to debug the TTX decoder 100 and the second whole. A cable 21 connected to the system 200 and an address line Ad0-Ad7 and a data line D0-D7 of the cable 21 are connected to each other to transmit / receive data to / from the TTX decoder 100 in both directions. The first buffer 22 and the second buffer 23 to be buffered, and the cable 21 of the TTX decoder 100 is connected to the output signal of the control bus (P0-Pn) through the cable 21 A ROM 28 which reads the program data for debugging the TTX decoder 100 by receiving a read control signal from the ROM 28 and stores the debugging program value system operating program data, the second buffers 22 and 23 and The ROM 28, the address bus (Ad0-Ad7) and the data bus (D0-D7) Therefore, a RAM is received and stored randomly by the control signal through the control buses P0-P7 and temporarily stores the test data according to the state data and debugging of the TTX decoder 100 ( 29) and parallel data as serial data or vice versa in accordance with the data flow of the data transceiver RS-232C input / output in the second data buffer 34 in accordance with a control signal generated from the control buses P0-Pn. Selected and the control unit 35 for generating a control signal to send or receive to the control, and the control bus (P0-Pn) of the cable 21 and the processor 27 to be described later is connected to the main processor of the TTX decoder 100 And a dip switch 25 to which a user's selection signal is applied to enable or disable the processor of the debug system 200, and the ROM 28 and the RAM 29 as processors of the debug system 200. ) And 1,2 It is connected between the fur (22, 23) and the address bus (Ad0-Ad7) and data bus (D0-D7), and the control bus (P0-Pn) is connected between the dip switch 25 to control the entire system and the dip switch A processor 27 for receiving and processing program data for debugging the TTX decoder 100 according to an externally applied signal from the processor 25 and outputting control signals and debugging processing results as data; and the first buffer 22 Is connected to the input / output terminals D0--D7 and the ROM 28, the RAM 29, and the address bus Ad0-Ad7 of the processor 27 in accordance with the address signal through the address bus Ad0-Ad7. Chip selector stage for selecting the ROM 28, RAM 29 and the selection and control unit 35

An address decoder 24 for generating a control signal of the switch; a switch 26 for selecting a baud rate (transmission rate: 9600bps, 4800bps, 120-bps, 300bps) required for data transmission from the terminal by a user; And an oscillation and division circuit 30 connected to the control bus P0-Pn to provide a basic clock for driving the debug system 200, and between the oscillation and division circuit 30 and the switch 26. A bower selector 31 connected to a control bus P0-Pn for selecting a transmission speed by selecting an oscillation frequency output from the oscillation and frequency division circuit 30 according to the selection of the switch 26; The frequency divider divides the baudrate frequency corresponding to the transmission speed selected by the bower selector 31 from the signal inputted through the control bus P0-Pn and connected to the control bus P0-Pn. 32, the first buffer 23, the processor 27, A second dade buffer 34 connected to the data buses D0-D7 of the RAM 29 and buffering the input / output data of the user side under the control of the selection and control of the controller 35; Transmitter 36 and RS-232C of the user terminal 300 to convert the parallel data output and connected to the data buffer 34 in series and to transmit to the user terminal 300 side through a line of RS-232C connection method The receiver 37 converts the serial data input through the connection method line into parallel data and inputs it to the second data buffer 34 of the debug system 200, and receives the clock signal divided by the divider 32. And a clock generator 33 for generating a clock for synchronizing with the speed of serial transmission and reception of data required by the second data buffer 34.

3 is a flowchart according to the present invention, where (3a) is a main flow chart according to the present invention, and (3b) is a subflow chart specifically showing the CVDG test step of step (3d) of (3a).

Menus to be selected by the user to initialize parts of the system and to test Prefix processors, which are Color Video Display Generatar (CVDG), Random Access Memory (RAM), Digital Teletext Preccssor (DTP), and TTX data formats. A first process of checking the selection key (AD) input by displaying the method; and a second process of processing according to the corresponding test program when the selection key (AD) input specified in the first process is present; In the process, when there is no "ESC" key input, the test menu is repeated to perform a test according to the corresponding test mode, and when there is an "ESC" key input, a third process is completed.

(3b) is a detailed flowchart of the CVDG test process by inputting the "A" selection key in the test mode of the second process in FIG. 3A, and according to the "1" or "2" key input in the CVDG test mode. The first step of searching for interface toggle and set scroll test mode selection keystrokes, and transfers a value of a predetermined number of three times of " 1 " The value of the sixth bit DR6 and the seventh, fifth, fourth, and third bit DR4 and DR3 of the switch register is set to "1", and the values of the other bits DR2-DRψ are unrelated. t care) and check whether there is a carriage return key (ENTER) input, and if there is a carriage return key input in the second step, the sixth bit (DR6) is disconnected and the carriage return key input is absent. A third step of checking whether there is an " ESC " key input; The fourth step of transferring the predetermined (number 3) register value to the Y scroll register and outputting data to display "ENTER SCROLL OFFSET [XX]", and then searching whether the key input is a value within 00 to 262. In the fourth step, when the value is not within 00 to 262, the "ENTER SCROLL OFFSET [XX]" is continuously displayed, and when the value is 00 to 262, the fifth step key scrolls the screen and waits for a carriage return key input.

Therefore, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3 described above. When the user operates the dip switch 25 from the outside while the system is turned on, the processor 27 controls the control bus ( In response to the manipulated input of the dip switch 25 through P0-Pn, the processor 27 resets each part of the system to the initial state in step 3a.

In order for the processor 27 to perform an initialization process, the processor 27 outputs a predetermined address signal through the address bus Ad0-Ad7 and decodes the address decoder 24 to select the output terminals Q1-Q2. A control signal for chip-selecting the controller 35, the ROM 28, and the RAM 29 is output.

Then, the read / write control signal and the address signal through the address bus Ad0-Ad7 are inputted to the ROM 28 through the control bus P0-Pn of the processor 27, and the TTX decoder built in the ROM 28 ( The debugging program of 100) is moved to RAM 29 and stored.

In addition, the RAM 29 is an address and data signal generated through the address bus Ad0-Ad7 and the data bus D0-D7 in the processor 27 and a write control signal output through the control bus P0-Pn. This temporarily stores the program data of the ROM 28 in the RAM 29.

Then, the second buffers 22 and 23 are controlled by the control signals of the control buses P0-Pn generated by the processor 27 to connect various types of information generated from the TTX decoder 100 to the cable 21. Buffered in the first and second buffers 22 and 23 via the address buses D0-D7 and Ad0-Ad7, and then chip-selecting the RAM 29 according to the decoding of the address decoder 24 and the processor 27. Under the control of the RAM 29, the TTX decoder 100 is stored in another area in which the debugging program is embedded.

In the process (3b), the processor 27 reads and processes the debugging program of the TTX decoder 100 from the RAM 29 under control. The resultant data is then input to the second data buffer 34.

The second data buffer 34 receives a clock from the clock generator 33 to serially convert the parallel data for transmission to be transmitted to the terminal 300 through the transmitter 30, and then selects and selects the controller 36. Is processed by receiving a control signal for converting the transmission data in parallel.

The data converted in series from the second data buffer 34 is input to the user terminal 300 connected to the RS-232C line through the transmitter 31 so that the user A; CVDG test, B, RAM test, D; DTP test, D; One test mode during the prefix process test is displayed on the monitor of terminal 300 for selection by A-D key input.

When the user inputs one of the AD keys through the keyboard at the terminal 300, the user inputs the second data bus 34 through the receiver 37, and at this time, the second data bus is controlled by the selection and control of the controller 35. The input data of (34) is converted into parallel and input to the processor 27.

At this time, the processor 27 checks whether the output data of the second data buffer 34 is the A-D key through the data buses D0-D7 as shown in (2c), (3e) and (3i).

For example, when the user 300 inputs the user "A" in the terminal 300, the processor 27 executes the CVDG test in step 3d.

The CVDG test of step (3d) will be described in detail with reference to FIG. 3 (b).

In the CVDG test, the processor 27 inputs the data into the second data buffer 34 so that the user can select 1: interface coggle and 2: set scroll test.

The second data buffer 34 converts the parallel data input by the control signal output from the selection and control unit 35 into serial and inputs the terminal 300 through the RS-232C line through the transmission unit 36. Display on the monitor.

The user can view the monitor of the terminal 300 and input the "1" or "2" key. For example, the interface is toggled, the "2" is entered, and the set scroll test mode is selected.

When the selected " 1 " or " 2 " input data is input to the second data buffer 34, the data input to the second data buffer 34 is converted in parallel according to the selection and the control of the controller 35. It is inputted by (27). At this time, the processor 27 checks whether the "1" or "2" buffer key is input from the terminal 300 in steps 3n and 3o.

In the process (3n), when the key is "1", the processor 27 controls the RAM 29 to read the third register substitute, which stores the value received from the TTX decoder 100, and transmit the read to the switch register (39). In the process, the 6th bit (DR6) is transferred to the switch register, and the value of the 6th bit (DR6) is set to "1". The value of DR3) is set to "1" and the value of 2 bits-0 bits (DR2-DR0) is treated as an unrelated condition.

Then, the processor 27 inputs whether the key data inputted from the terminal 300 is a carriage return key or an "ESC" key through the second data wave 34 to search in steps 3S and 3E.

If it is confirmed by input of the carriage return key in step (3S), invert () the value of the 6 bit (DR6) in step (3t), and execute again from step (3r), and if "ESC" is input, the process is performed. To finish.

However, if the processor 27 has a "2" key input in the process (30), it controls the RAM 29 to convert the key register 3, which is the area where the state value of the TTX decoder 100 is stored, into the Y scroll register (3u). In step (3v), the processor 27 outputs data for display of 'ENTER SCROLL OFF SET [XX]' and displays the data for the second data buffer to display the state on the monitor of the terminal 300. Enter in (34).

As described above, the second data buffer 34 converts the parallel data into a serial unit under the selection and the control of the control unit 35 so as to be input to the terminal 300 through the transmitter 3b for display.

The processor 27 waits for keyed data input through the keyboards of the terminal 300 through the transmitter 3b and the second data buffer 34 in step 3w.

Check if the key input value is for the 0-262 line for jump scan.

In step (3w), when there is a selection key input for 0-262 lines, scroll screen control data is sent to the monitor of the terminal 300 in step (3x). It outputs through and scrolls the state of the monitor of the terminal 300 to 262 lines.

As described above, the processor 27 waits for an input corresponding to a carriage return in step 3y, and returns when there is a carriage return key input. In step 3k, the processor 27 ends the processing.

As described above, it is easy to find out the abnormality of TTX decoder processor and RAM or other processor by using debug system, and it is possible to directly communicate with user by connecting to terminal through RS-232C input / output line. There is an advantage to this.

Claims (1)

In the teletext (TTX) system debugging system, a cable 21 for connecting a 40-pin cable to the host processor of the TTX decoder 100 to connect the TTX decoder 100 and the debug system 200, and the cable A first buffer 22 and a second buffer 23 which are connected to the address line Ad 0 -Ad 7 and the data line D 0 -D 7 of 21 to buffer the transmission / reception data with the TTX decoder 100 in both directions; Debugging for debugging the TTX decoder 100 by receiving a read control signal from an output signal of a control bus P0-Pn through a cable 21 connected to the cable 21 with the TTX decoder 100. ROM 28, which reads the program data and stores the debugging program and system operating program data, and the second buffers 22 and 23, the ROM 28, the address buses (Ad0-Ad7), and the data bus. Control signal connected to the (D0-D7) through the control bus (P0-Pn) RAM 29 that receives the program into the ROM 28 and randomly stores therein the RAM 29 temporarily storing the state data of the TTX decoder 100 and the test data according to the debugging, and from the control bus P0-Pn. Selection and control unit for generating a control signal to send or receive parallel data in serial data or vice versa in accordance with the data flow of the RS-232C input / output method when transmitting and receiving data in the second data buffer 34 according to the generated control signal ( 35) and a dip connected to the control bus P0-Pn to which a user's selection signal is applied to enable or disable the main processor of the TTX decoder 100 and the processor of the debug system 200. The switch 25, the ROM 28, the RAM 29, and the first and second buffers 22 and 23, the address bus Ad0-Ad7 and the data bus D0- as processors of the debug system 200. D7) is connected between the dip switch (25) The control bus (P0-Pn) is connected to control the entire system and receive and process the program data for debugging of the TTX decoder 100 by a signal applied from the outside from the dip switch 25 to control signals and debugging A processor 27 for outputting the result as data, and an input / output terminal D0-D7 of the first buffer 22 and an address bus (Ad0-Ad7) of the ROM 28, the RAM 29, and the processor 27. Is connected to the address to generate a control signal of the chip selector stage CS for selecting the ROM 28, the RAM 29 and the selection and the control unit 35 according to the address signal through the address bus Ad0-AD7. It is connected with the control bus (P0-Pn) and the switch (26) which selects the baud rate required for the terminal and data transmission by the de-corner (24), and is operated by a user, and is used to drive the debug system (200). An oscillation and division circuit 30 which provides the necessary basic clock; The transmission speed is selected by selecting the oscillation frequency output from the oscillation and division circuit 30 according to the selection of the switch 26 by being connected to the control bus P0-Pn between the circuit 30 and the switch 26. A bow that is connected to the bow selector 31 and the control bus P0-Pn and that is adapted to the baud rate selected by the bowator selector 31 from a signal input through the control bus P0-Pn. A divider 32 that distributes a predetermined rate frequency, and connected to the first bus 23, the processor 27, the ROM 28, and the dada buses D0-D7 of the RAM 29 are connected to the user. RS-232C connection method by converting the second data buffer 34 which buffers the input / output data of the input / output data according to the control of the controller 35 and the parallel data which is connected to the second data buffer 34 and outputted in series. Transmitter 36 and the user terminal 300 to transmit to the user terminal 300 side through the line of The receiver 37 converts the serial data input through the RS-232C connection type line into parallel data and inputs it to the second data buffer 34 of the debug system 200, and is divided by the divider 32. And a clock generator 33 for receiving a clock signal and generating a clock for synchronizing with the speed of serial transmission and reception of data required by the second data buffer 34. Debug system.

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