KR900005445A - Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits - Google Patents

Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits Download PDF

Info

Publication number
KR900005445A
KR900005445A KR1019880012700A KR880012700A KR900005445A KR 900005445 A KR900005445 A KR 900005445A KR 1019880012700 A KR1019880012700 A KR 1019880012700A KR 880012700 A KR880012700 A KR 880012700A KR 900005445 A KR900005445 A KR 900005445A
Authority
KR
South Korea
Prior art keywords
redundant
data
ultra
cell matrix
redundancy scheme
Prior art date
Application number
KR1019880012700A
Other languages
Korean (ko)
Inventor
김주한
Original Assignee
이만용
금성반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이만용, 금성반도체 주식회사 filed Critical 이만용
Priority to KR1019880012700A priority Critical patent/KR900005445A/en
Publication of KR900005445A publication Critical patent/KR900005445A/en

Links

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음No content

Description

초고집적/대용량 메모리 집적회로에서 리던던시 스킴 방법 및 그 장치Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 리던던시 스킴을 4메가 디-램에 적용한 예.1 is an example of applying a conventional redundancy scheme to a 4 mega di-ram.

제2도는 본 발명의 리던던시 스킴의 블록도.2 is a block diagram of a redundancy scheme of the present invention.

제3도는 본 발명의 리던던시 스킴을 4메가 디-램에 적용한 예.3 is an example of applying the redundancy scheme of the present invention to a 4 mega di-ram.

Claims (2)

메인 메모리 셀 블럭과 리던던트 메모리 셀 블럭을 별도의 블럭으로 배치하고 리던던트 메모리 셀을 구분하여 컬럼 리페어와 로우 리페어가 되게하고 또한 더블 비트 혹은 싱글 비트를 리페어 되게 하며 데이타를 라이트 할때는 메인 메모리 셀 블럭과 리던던트 메모리 셀 블럭에 동시에 라이트하고 리미드 할때는 두 블럭에서 동시에 리이드하여 데이타 라인 콘트롤 신호를 받은 데이타 셀렉터(9)의 선택에 의해 레이저 리페어가 이루어지도록 하는 초고직접/대용량 메모리 집적 회로에서 리던던시 스킴 리페어 방법.The main memory cell block and the redundant memory cell block are arranged in separate blocks, and the redundant memory cells are divided into column repairs and row repairs, and double or single bit repairs are performed. When writing data, the main memory cell blocks and redundant ones are written. Redundancy scheme repair method in an ultra-high direct / large-capacity memory integrated circuit in which a laser repair is performed by selection of a data selector (9) receiving data line control signals by simultaneously reading and writing to a memory cell block at the same time. 어드레스 버퍼(1)로부터 프리디코더(2)를 지난 어드레스(A)는 퓨우즈(7,7')와 메인 셀 매트릭스(3)의 디코더(4,4')의 입력이 되고, 데이터 라인 콘트롤(8)로부터 신호를 받아, 메인 셀 매트릭스(3) 또는 리던던트 셀 매트릭스의 데이터를 선택하는 데이타 라인 셀 렉터(9)는 출력버퍼(10)를 통하여 데이타를 리이드하고 입력버퍼(10')를 통하여 메인 셀 매트릭스(3)와 리던던트 셀 매트릭스(5)에 라이드 하도록 구성한 것을 특징으로 하는 초고집적/대용량 메모리 집적 회로에서 리던던시 스킴 장치.The address A past the predecoder 2 from the address buffer 1 is input to the fuses 7 and 7 'and the decoders 4 and 4' of the main cell matrix 3, and the data line control ( 8, the data line selector 9, which selects data of the main cell matrix 3 or the redundant cell matrix, leads the data through the output buffer 10 and through the input buffer 10 '. Redundancy scheme device in an ultra-high density / large-capacity memory integrated circuit, characterized in that it is configured to ride in the cell matrix (3) and the redundant cell matrix (5). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880012700A 1988-09-30 1988-09-30 Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits KR900005445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880012700A KR900005445A (en) 1988-09-30 1988-09-30 Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880012700A KR900005445A (en) 1988-09-30 1988-09-30 Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits

Publications (1)

Publication Number Publication Date
KR900005445A true KR900005445A (en) 1990-04-14

Family

ID=68158153

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880012700A KR900005445A (en) 1988-09-30 1988-09-30 Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits

Country Status (1)

Country Link
KR (1) KR900005445A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5988510A (en) * 1997-02-13 1999-11-23 Micron Communications, Inc. Tamper resistant smart card and method of protecting data in a smart card
US6273339B1 (en) 1999-08-30 2001-08-14 Micron Technology, Inc. Tamper resistant smart card and method of protecting data in a smart card

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5988510A (en) * 1997-02-13 1999-11-23 Micron Communications, Inc. Tamper resistant smart card and method of protecting data in a smart card
US6068192A (en) * 1997-02-13 2000-05-30 Micron Technology, Inc. Tamper resistant smart card and method of protecting data in a smart card
US6273339B1 (en) 1999-08-30 2001-08-14 Micron Technology, Inc. Tamper resistant smart card and method of protecting data in a smart card

Similar Documents

Publication Publication Date Title
KR950024220A (en) Redundant circuit device
KR940012406A (en) Low redundancy circuit with high integration and reliability and semiconductor memory device having same
KR900019028A (en) Semiconductor Memory Device with Redundant Block
FR2688328B1 (en) ROW REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE FOR REPAIRING OR REPLACING A DEFECTIVE CELL OF A MEMORY CELL ARRAY.
KR930006737A (en) Random access memory device
KR900002332A (en) Semiconductor memory with redundant circuit for defect repair
KR890015280A (en) Mask ROM
KR930018593A (en) Semiconductor memory
KR840008073A (en) Semiconductor memory
KR950025788A (en) A semiconductor memory device having a redundant decoder that can be used for test procedures of redundant memory cells
KR970013336A (en) Semiconductor storage device
DE69602013D1 (en) PARALLEL PROCESSING REDUNDANCY DEVICE AND METHOD FOR FASTER ACCESS TIME AND SMALLER MATRICE SURFACE
KR960042765A (en) Memory Cell Test Control Circuit and Method of Semiconductor Memory Device
KR890015132A (en) Dynamic random access memory and its margin setting method
KR940022845A (en) Semiconductor memory and redundant address writing method
KR940026948A (en) Fault Remedy Circuit
KR930020678A (en) Semiconductor memory
KR910020733A (en) Static memory
KR940010113A (en) Fault Relief Circuit in Semiconductor Memory Device
KR970012708A (en) Integrated semiconductor memory device
KR890004326A (en) Semiconductor memory device
US6072735A (en) Built-in redundancy architecture for computer memories
KR900005445A (en) Redundancy Scheme Method and Apparatus for Ultra-Integrated / Large Memory Integrated Circuits
US5748526A (en) Circuit for repair of flash memory cells and a method of repair
US5956276A (en) Semiconductor memory having predecoder control of spare column select lines

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination