KR900005164B1 - Code-conversion method of different coded exchanges - Google Patents

Abstract

A code conversion system comprises; a control signal generator (10) for generating read/write control signals, various clock signals and distributed signals; an input conversion section (20) for converting received serial PCM data into 8-bit parallel data; a code conversion section (30) comprising the first and second conversion region to store A-law and -law data and to convert the code/ a parity check (40) for cchecking the parity state of generated data; an address generator (50); an address selector (60); a time memory (70) for compensating the timing of input/output time slots; a function checker (80); and an output conversion section (90) for converting paralele PCM data into serial A-law and -law PCM data.

Description

Code converters of exchanges with different coding schemes

1 is a system diagram of the present invention.

2 is a block diagram of the present invention.

3 is a concrete block diagram of FIG.

4 is a map configuration diagram of the code conversion unit in FIG.

5 is an operating waveform diagram of FIG.

6 is an operational waveform diagram of an address generator of FIG.

* Explanation of symbols for main parts of the drawings

10: control signal generator 20: input conversion unit

30: code conversion unit 40: parity check unit

50: address generator 60: address selector

70: timing adjusting unit 80: function checking unit

90: output converter

The present invention relates to a code conversion device, and more particularly, to a code conversion method and a control device that can be mutually matched so that data can be shared between telephone exchanges using different coding methods. In general, in order to convert an analog signal into a digital signal, sampling and quantizing the analog signal are performed. Sampling divides a continuous input signal into a time domain and quantization converts the sampled signal into an amplitude domain. The dividing operation creates a step waveform. Therefore, if the quantization step is small, the quantization noise is small, but the number of steps is increased, and the number of digits of the encoding and the encoding apparatus are complicated.

To compensate for these drawbacks, an uneven quantization method is used, which means that the quantization noise-to-signal ratio is large at small amplitudes but not much at large amplitudes, so that the quantization steps are small at large amplitudes and large at large amplitudes. The quantization method that corresponds to the steps. That is, when a transmitter compresses a signal using a compressor and outputs the signal, the receiver expands and outputs a signal compressed by an expander. In the companding method, there are A-law method and μ-law method. The CEPT method (Conference European de Postes et Teleccmunication) adopting the A-law method is used in most countries including Europe, μ The NA (North America) method, which adopted the -law method, is used in the United States, Japan, and Korea. In the A-law CEPT method and the μ-law method, the PCM data sampling frequency (8KHz) and the number of bits per code word are the same, but the quantization companding method is different and the number of channels is different. The International Telegraph & Telephone Consulative Committee simultaneously recommends two PCM multiplexing schemes. Digital paths between countries that adopt different encoding laws are coded according to the A-law scheme. Since the signal must be transmitted, the countries using the μ-law method had to have a means to convert to the A-law method, and the interface could be easily matched during the exchange using different PCM encoding methods. There was a problem that there was no device.

Accordingly, an object of the present invention is to provide a conversion apparatus capable of mutually exchanging information of an exchange period using different encoding schemes.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1A is a system diagram of the present invention, wherein the first and second exchangers 1 and 2 processing different encoded data and the different PCM data which are outputs of the first and second exchangers 1 and 2 are mutually interchangeable. It is composed of a code conversion board (3) to match, and assumes that the code conversion board (3) is built in the first exchanger (1) as shown in Figure 1b, the first exchanger (1) is PCM data of the μ-law method It is assumed that the second exchanger 2 outputs law type PCM data.

The input / output process of the data coded by the present invention will be described with reference to FIGS. 1a and b. The code conversion board (3) for inputting the PCM data of the first exchanger (1) using the µ-law method is G711 (Rec.G711) which recommended the µM-law PCM data by the Telegraph Telephone Advisory Committee (CCITT). According to the inter-conversion table (μ-law to A-law, A-law to μ-law Conversion table) of A-law type PCM data, the converted data is converted into A-law type second exchanger (2 ) At this time, the A-law type PCM data output from the second exchanger 2 is input to another input port of the code conversion board 3, and the code conversion board 3 stores the input A-law type data μ. -Law data is converted and output from the first exchanger (1). Accordingly, the outputs of the first and second exchangers 1 and 2 that output PCM data having different coding schemes as shown in FIG. 1a can be coded into one code conversion board 3 to input and output. If only one of the two exchanges 1 and 2 having the transmission system is installed, data of different encoding methods can be interfaced, so that mutual information can be exchanged.

FIG. 2 is a block diagram of the present invention. The system clock and frame synchronization signals are input to generate write / lead control signals and various clock signals, and the system clocks are divided in the frame synchronization period to divide the first to eighth divided signals. Receives a control signal generator 10 and a serial PCM data of the μ-law method to the first input terminal, and receives the serial PCM data of the A-law method to the second input terminal, the control signal generator 10 The input conversion 20 converts 8-bit parallel data according to the clock signal of < RTI ID = 0.0 >, and < / RTI > And a second conversion area for storing one corresponding μ-law data, wherein the conversion area is selected by a predetermined division signal of the control signal generation unit 10 and corresponds to the output data of the input conversion unit 20. Data is read at the The parity check unit 40 which receives the output of the code conversion unit 30 and the code conversion unit 30 which performs the conversion, generates parity of 1 bit, and analyzes the parity state of the output data to check for abnormality. And a write agent for receiving the first to eighth divided signals of the control signal generator 10 and outputting the first to eighth divided signals to the read first address and delaying the first address for a predetermined time slot for compensation according to a circuit delay. The mode is selected by the address generator 50 for generating two addresses, the address selector 60 for selectively outputting the first and second addresses for each time slot period, and the write / read control signal. By storing and outputting 8-bit code conversion and parity bits at the output address positions of the address selector 60, the timing is compensated so that the input time slot and the output time slot are the same. Is a time memory 70, a function test unit 80 for displaying an error signal when the parity check unit 40 generates an abnormal signal, and converts the code-converted timing-adjusted parallel PCM data into serial PCM data to A first output terminal. An output converter 90 outputs -law PCM data and outputs μ-law PCM data to the second output terminal.

The code conversion board 3 is accommodated in the digital trunk line interface device to perform the code conversion operation between the digital concentrator device on the subscriber side and the digital trunk line interface device. When receiving the A-law-coded data, the code conversion board 3 is used. In order to convert the encoded data into the L-law encoded data and convert the encoded data into the A-law encoded data, the encoded data is exchanged between the exchanges using different transmission systems.

The PCM data of μ-law is input to (101) line, and the PCM data of A-law is input to (102) line, and the (101) and (102) lines are composed of four sub highways. The conversion unit 20 converts the serial PCM data input to the eight subhighways into parallel PCM data and applies it to the address of the code conversion unit 30. It is also assumed that a clock signal of 4 MHz is input to 111, a clock signal of 2 MHz to 112, and a master reset signal that is a frame synchronization signal is input to 113. Multiplexed serial PCM data of the A-law method is applied through the input lines 101 and 102 and the A-law method through the 102. In addition, the control signal generator 10 inputs 4,096 MHz, 2,048 MHz and a frame synchronization signal as a master reset signal, and divides and outputs 2,048 MHz as an address by eight, and outputs a signal of 512 MHz to the code conversion unit 30. Is applied to the most significant bit address of and output as the first and second conversion region selection signals. That is, the code conversion unit 30 is divided into a first conversion region for converting the μ-law PCM data and a second conversion region for converting the A-law PCM data into the μ-law PCM data. It becomes a signal for selecting the first and second conversion regions.

Therefore, in the 8-bit parallel of the input conversion unit 20, the code conversion unit 30, which inputs the address signal for code conversion, inputs the A-law data stored in the corresponding address using the received data as the address in the first area. When the A-law data is input, the second region outputs μ-law data in the same manner as described above, and the converted data is written to a predetermined region of the time memory 70 and output to the parity check unit 40. Outputs the parity bit corresponding to the coded data.

At this time, the control signal generator 10 generates a divided signal for sequentially writing and reading the code conversion data of the code converter 30 into the time memory 70, and the address generator 50 generates the control signal. The division signal of the generator 10 is input to generate a first address for sequentially writing code conversion data to the time memory 70 and a second address which is a lead address for compensating a delay time through a circuit. When the input PCM data is code-transformed and output, the input PCM data and the code-converted PCM data have different time slots due to a delay according to the circuit configuration, so that the receiving and output PCM data have the same time slot. Adjust it. In this case, the address selector 60 selects the first and second addresses according to the state of the write enable signal, and supplies the first and second addresses to the time memory 70. At this time, the PCM data and reads written to the time memory 70 are read. A difference of about 1 frame occurs between the PCM data.

The reason for controlling the read timing in the time memory 70 is to compensate for propagation delay between circuit elements as described above, and thus to output the same time slot as one frame before the input time slot. To control.

At this time, the function check module 80 monitors the write enable signal of the time memory 70 and the parity signal of the conversion data to drive the LED in the event of an abnormality, and further, to dismount the code board 3. Monitors and outputs alarm signal to Alarm Handing. The code conversion data output from the time memory 70 by the first address signal of the dress selector 60 is composed of 9 bits, of which 1 bit is a parity bit and is output to the parity check unit 40 to convert the corresponding parity bit. After detecting and converting the 8-bit pure conversion data into the output conversion unit 90, the converted data is converted into serial data, and A-law data is output to the first output terminal 103, and the second output terminal 104 is output. As for the data of μ-law method is output.

3 is a detailed circuit diagram of the present invention, which is composed of an inverter 11-16, a counter 17, a NAND gate 18, and a latch 19, and includes a 4.092 MHz (CP1), 2.048 MHz (CP2), and frame synchronization signal. A control signal generator 10 for generating a read / write control signal and various clock signals and dividing the 2.048 MHz (CP2) signal to generate the first to eighth divided signals CP3-CP10; It consists of a first buffer 21, a serial converter 22 and a first latch 23, to receive the μ-law serial PCM data to the first to fourth sub-highway, and to the fifth to eighth subhighway An input converter 20 for receiving A-law serial PCM data and converting the serial PCM data into 8-bit parallel data with a clock of 2.048 MHz (CP2); And a first conversion area storing A-law data and a second conversion area storing μ-law data corresponding to A-law data 1: 1. A first or second conversion area is selected by the third division signal CP5 with 8 bits of parallel data of the first signal and 256 kHz signal which is the main signal CP5 of the third part of the control signal generator 10 as an address. And a code conversion unit 30 for outputting conversion code data corresponding to the 8-bit parallel data, a parity generator 41, and a parity detector 42. The parity according to the output of the code conversion unit 30 is obtained. And a parity check unit 40 for checking the parity of the code conversion data being read and indicating whether there is an abnormality, and a latch 51-57, to read the first to eighth divided signals CP3-CP10. By the address generator 50 generating the second address for the write address, which is generated at the first address as an address and is delayed by a predetermined time slot to output to the same time slot as the input time slot, and by the 2.048 MHz (CP2). Select the first and second address An address position selected from the address selector 60, the second latch 71, and the memory 72, 73, the mode being selected by the read / write control signal, and output from the address selector 60. A time memory 70 for controlling timing so as to store and output 9-bit data of code conversion and parity in the same time slot data having a difference of one frame between input and output PCM data, and a monostable multivibrator ( 81, a latch (82, 83), the end gate 84 and the LED (85), the parity check unit 40, the functional inspection unit 80 to drive the LED 85 when the abnormal signal is generated to display the abnormal state ), And a third latch 91, a parallel-to-serial converter 92, and a second buffer 93, converting the coded parallel PCM data into serial PCM data to convert the first to fourth subhighway A-. Output the law PCM data and transfer the μ-law PCM data to the fifth to eighth subhighways. It consists of an output converter 90 for outputting.

FIG. 4A is a diagram of a memory map of the code conversion unit 30 in FIG. 3. The first conversion area is an area storing A-law data corresponding to 1: 1 in μ-law data, and a second conversion area. The area is an area storing μ-law data corresponding to 1: 1 in the A-law data, and FIG. 4B is an example of conversion of the code change unit 30.

FIG. 5 is an operation waveform diagram of FIG. 3, which shows that the corresponding timeslot data of all frames is outputted when the current arbitrary timeslot data value is input. FIG. As the output waveform diagram of the generation unit 50, the output of the write address and read address of the time memory 70 is shown.

The present invention will be described in detail with reference to FIGS. 3, 4, 5, and 6 in the above-described configuration.

Inputs of the first buffer 21 are the first to fourth highways SHW1-SHW4 outputted from the demultiplexer board of the digital subscriber concentrator, and the fifth to eighth outputted from the CEPT digital relay device. The serial PCM data on the subhighway (SHW5-SHW8) is input and buffered. Therefore, the serial PCM data on the 1st-4th subhighway (SHW1-SHW4) is the μ-law type PCM data, and the serial PCM data on the 5th-8th subhighway (SHW5-SHW8) is the A-law type data. It can be seen that.

At this time, in the timing diagram of FIG. 5, (5a) is a signal of 4,096MHz (CP1) input through the terminal 111, (5b) is a signal of 2,048MHz (CP2) input through the terminal 112, 5c is a signal of cp2 through the inverter 12, 5d is a signal of cp2 through the inverters 12 and 16, and 5e is an output of the inverter 13 by 4,092 MHz (CP1). The latch output is the output of the latch 19, and 5f is the inverted output of the latch 19.

A data transmission clock of a system such as (5a)-(5f) of FIG. 5 is generated by the control signal generator 10. The signal of (5e) is applied as a clock signal of the latch 56 and the inverter 15 Is applied as the clock signal of the first latch 23 and the second latch 71, the signal of (5f) is applied as the clock signal of the latch 57, the (5d) signal is the address selector 60 Is applied to the selection control signal of < RTI ID = 0.0 >) < / RTI > and the clock signal of the third latch 91, and the signal CP2 of (5c) is applied as the clock signal of the parallel-to-serial converter 92.

Therefore, the data of the input ports Bi1-Bi4 of the first butter 21 are the serial PCM data of the µ-law method. At this time, the data of the input port Bi5-Bi8 is A-law serial PCM data, and the PCM data output of the first buffer 21 such as (5g) is the input port 8i1-Si8 of the serial-to-parallel converter 12. ), The serial PCM data is converted into 8-bit parallel data by the 2048MHz clock and output to the first latch 23. As shown in (5h), the propagation delay time is delayed by about 9 times slots than the input time slot. (Propagation Delay Time). Then, the first latch 23 inputs 8-bit parallel data of the serial-to-parallel converter 22 and 256 KHz (CP5) for selecting the conversion area of the code conversion unit 30 during the output of the counter 17. CP5 becomes a signal for selecting the first transform region of the µ-law / A-law and the A-law / µ-law second transform region of the code conversion unit 30. The code conversion unit 30 is a PCM code 256 words (Word) by the μ-law companding method (CCITT Rec.G711) recommended by the International Telegraph Advisory Committee (PCIT) and PCM by the A-law companding method. A 256-word code conversion table is stored as shown in FIG. 4A, and 0-255 of the address of the code conversion unit 30 is a received μ-law data as an address, and A- at a position corresponding to 1: 1. The law conversion data is stored, and the 256-511 address stores the A-law data as an address and stores the μ-law conversion data at a position corresponding to 1: 1. Therefore, 0-255 is the first conversion area for converting μ-law data into A-law data, and 256-511 is the second conversion area for converting A-law data into μ-law data. .

Therefore, the code conversion unit 30 inputs a 9-bit signal of the first latch 23 to input dual 8-bit PCM data as an address signal, and a 1-bit 256KHz (CP5) signal is a control signal for selecting a conversion region. Enter

4B is an example of code conversion of the code conversion unit 30. When 256KHz (CP5), which is a 1-bit control signal of the 9-bit address input signal, is low (“0”), μ-law is shown in the first conversion area. Shows that the data of A-law is converted to the data of μ-law in the second conversion area when the control signal is high ("1"). Is output as

In order to generate an address signal for writing and reading the output of the code conversion section 30 to the memories 72 and 73, the counter 17 inputting 2.048 MHz (CP2) outputs this signal as shown in FIG. It divides at 8KHz (CP10) at MHz (CP3) and outputs it to the latch 56 for a lead address, and another end of the output is input to the latches 51-55 to generate a write address. As described above, a difference of about 9 timeslots occurs between the PCM data of the input timeslot and the PCM data written to the time memories 72 and 73. Therefore, the lead address is about 9 times slots faster than the write address to generate the light address 9 times slot later than the lead address.

The operation waveform diagram of FIG. 6B is a waveform diagram of the write address signal, and the latch 51 inputs 512 KHz (CP4) such as (6b) as the clock at 1.024 MHz (CP3) such as (6a), as shown in (7b). The latch 52 inputs 256KHz (CP5), such as 6c, to the inverted output of the latch 51 as a clock and outputs the same as (7c), and the latch 53 inverts the latch 52. Input the 128KHz (CP6), such as (6d), as the clock, and invert the output as shown (7d), and the latch 54 inputs 64KHz (CP7), such as (6e), as the clock of the output of the latch 53. The output terminal 7e is outputted to the output terminal, and the latch 55 outputs the inverted output of the latch 54 as a clock signal by inputting 32, 16, 8KHz (CP8-CP10) as (7f)-(7g). do. Therefore, the difference between the lead and the write address is 9 timeslots, and the relationship between the lead addresses and the 9 timeslots is as follows.

The signals of the write address and the read address shown in Table 1 differ from the address signals applied to the memories 72 and 73 to compensate for the propagation delay time of each device. Since the memory 72 and 73 are written through the delay time, the data of the frame is output immediately before the output time in consideration of the propagation time of each device. That is, the interval between the write and the read in the memories 72 and 73 has a difference of one frame.

At this time, the latch 56 outputs the lead address shown in Table 1 by the output of the latch 19 as shown in (5e), and the latch 57 as the clock signal as the inverted output of the latch 29 as shown in (5f). Outputs a write address as shown in Table 1, and the address selector 60 inputs the output of the latch 56 outputting the read address and the latch 57 outputting the write address in accordance with a signal of 2.048 MHz. As shown in (5m), the selector 56 outputs the latch 56 when the 2.048 MHz signal, which is the select signal, is the "low" signal, and selects and outputs the latch 57 when the input is the "high" signal.

In addition, the output of the NAND gate 18 such as (5l) which negatively multiplies 4,096 MHz and 2,048 MHz becomes a write / lead control signal of the time memories 72 and 73, and the read / write control signal is in a "low" state. The temporary memories 72 and 73 write the 8-bit code conversion data of the code conversion section 30 and the 1-bit signal of the parity generator 41 to the write addresses shown in Table 1 designated by the address selector 60. do. Thereafter, when the write operation is completed, the address selector 60 outputs the read addresses shown in Table 1 as shown in (5m), and the time memories 72 and 73 are used to record the previous frames recorded at the corresponding addresses. The data is read out as (5n) and output to the third latch 91, and the 8-bit code conversion data of the output of the third latch 91 as shown in (0) of FIG. 5 considering the propagation delay time is parallel. A single bit parity signal and 8 bits of parallel data are inputted to the converter 92 and converted into serial data, and the parity detector 42 is inputted to check the state of parity.

At this time, when an abnormal state occurs in the parity signal, the parity detector 42 outputs a "low" signal and is input to the latch 82, so that the output of the latch 82 becomes a "low" state and is applied to the AND gate 84. As a result, the LED 85 is driven to indicate an abnormal state. In addition, when an error occurs in the write / read control signal of the NAND gate 18, the control signal is output through the monostable multivibrator 81, which is a write mode signal (i.e., the NAND gate 28) within a predetermined period (3us). If the output of the "low" state does not occur, and outputs a "low" signal to drive the LED (85). The outputs of the monostable multivibrator 81 and the latch 82 function to monitor the write / lead control signals of the time memories 72 and 73 and the abnormal signals of the digital data, so that any one of them fails. When a failure occurs, the function fail signal is output to the alarm generation circuit and the LED is configured.

The parallel-to-serial conversion unit 92 which inputs the output of the third latch 91 outputted as (5o) converts the coded 8-bit parallel data into serial PCM data and delays the output as shown in (5p). Since the delay time is compensated for in the address, it can be seen that the same data of the previous frame identical to the time slot of the PCM data of the first buffer 21 currently input is outputted. The A-law data is converted into the second exchanger through the output port bo1-bo4 of the second buffer 93 after being input into the buffer 93, and the first port is output through the output port bo5-bo8. The μ-law data converted by the stirrer is output.

The above-mentioned matters are comprehensively described.

The code conversion unit 30 is a ROM memory, in which A-law and μ-law conversion data recommended to the CCITT are programmed. Among them, 0-255 addresses A-law data that corresponds 1: 1 with 256-level μ-law data. Is a μ-A conversion area where 256 is stored, and addresses 256-511 are A-μ conversion areas in which A-law data corresponding to 1: 1 A-law data of 256 levels is stored. Therefore, a serial-to-parallel converter converts the serial PCM data of the μ-law method, which is the output of the first exchanger 1, and the APC-type serial PCM data, which is the output of the second exchanger 2, into 8-bit parallel data. Code conversion unit 30 for inputting a signal of 256 kHz between the output of (12) and the output of counter 27 outputs the μ-law data as the A-law data using the input PCM data as the address. Is converted to μ-law data.

At this time, the time slot delay according to the circuit configuration occurs. This is because, after the input serial PCM data is converted to parallel PCM data, there is a delay of about 9 timeslots in the code conversion process.

Therefore, there is a difference of about 9 timeslots between the time slots of the PCM data applied to the serial-to-parallel converter 22 and the PCM data written to the time memories 72 and 73. Therefore, in order to match the input PCM data and the conversion PCM data outputting the parallel-to-serial converter 92 to the same time slot, the read address is adjusted 9 times faster than the write address. Therefore, the code conversion data applied to the memory 72, 73 is stored by the write address, and 9 timeslots early (that is, 247 timeslots are in a late state). When the read address is generated and the code conversion data of the entire frame is output, the time slot delay generated in the parallel-to-serial conversion process is compensated for, so that the serial PCM data and the output conversion unit 90 are applied to the input conversion unit 20. The transcoded serial PCM data output is delayed by one frame to have the same timeslot. In addition, when code data is converted, parity is inserted to detect an abnormality. When an abnormality occurs in the voice data or an error occurs in the write / lead control signal, the functional inspection unit 80 displays it.

As described above, by matching the communication device using the A-law method and the communication device using the μ-law method, it is possible to easily exchange information with each other, thereby meeting the standards for internationalization of communication. The advantages of both methods can be shared, and one board can simultaneously output and output the outputs of two other exchanges.

Claims (1)

In a code conversion apparatus of an exchange processing data having a different encoding method, a system clock and a frame synchronization signal are input to generate a write / lead control signal and various clock signals, and the system clock is divided by the frame synchronization period to generate a first clock signal. A control signal generator 10 for generating an eighth divided signal, a serial PCM data of μ-law type to a first input terminal, and an A-law serial PCM data of A-law type to a second input terminal; An input conversion section 20 for converting the 8-bit parallel data into a clock signal of the signal generator 10, and a first conversion region section for storing A-law data 1: 1 corresponding to μ-law data. And a second conversion area storing μ-law data corresponding to 1: 1 of the A-law data. The conversion area is selected by a predetermined divided signal of the control signal generator 10, and the input conversion part ( 20) vs output data The data is read at the corresponding position, and the code conversion unit 30 performs code conversion, and receives the output of the code conversion unit 30 to generate 1 bit parity, and analyzes the parity state of the output data. The parity check unit 40 checks the presence and absence of the first to eighth divided signals of the control signal generator 10 and outputs them to the first address for the read, and simultaneously compensates for the delay due to the circuit delay. An address generator 50 for generating a second address for writing with a predetermined time slot delay, an address selector 60 for selectively outputting the first and second addresses in a time slot period, and the write / read control. The mode is selected by the signal, and the 8-bit code conversion and parity bits are stored and output at the output address position of the address selector 60 to have a difference of one frame, and the input time slot and the output time slot are moved. A time memory 70 for compensating for timing, a function checking unit 80 for displaying an error signal when the parity check unit 40 generates an abnormal signal, and converting the code-converted timing-adjusted parallel PCM data into serial PCM data. A code conversion device of an exchange having a different encoding method, comprising: an output conversion unit (90) for outputting A-law PCM data to one output terminal and μ-law PCM data to a second output terminal.

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