KR900002909B1 - Semiconductor infergrated circuit - Google Patents

Abstract

The semiconductor integrated circuit for higher density comprises: base cells including a plural of functional devices formed on the semiconductor chips; cells perpendicular to the base cells; the first insulating layer formed on the semiconductor chips; a plurality of the first interconnections formed on the insulating layer; a plurality of the first opening holes for connecting the base cells and the insulating layer; the second insulating layer formed on the first interconnections; a plurality of the second interconnections formed on the second insulating layer.

Description

Semiconductor integrated circuit

1 is a chip plan view of a master slice LSI.

2 is a plan view of the basic cell of FIG.

3 is a cross-sectional view of the semiconductor chip of FIG.

4 is a symbol diagram of a logic gate block of a conventional example.

5 and 6 are views showing connection of input terminals of a logic gate block according to a conventional example.

7 and 8 are views showing the connection of the input terminal of the logic gate block for explaining the principle of the present invention.

9 is a circuit diagram of a four input multiplexer.

10 and 11 are connection diagrams each showing an embodiment of the present invention.

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit suitable for a high integration density master slice LSI.

In the master slice LSI, only the mask purchase corresponding to the wiring among the dozens of masks used in manufacturing the LSI is manufactured according to the developed variety to manufacture the LSI having the desired electric circuit operation.

Conventionally, the one disclosed in Japanese Patent Laid-Open Nos. 57-183048 and 57-4948 is shown in FIG. 1 as an example showing the structure of a general master slice LSI. The semiconductor chip 1 has a bonding pad and an output circuit region 2 at its outer circumference, and has a basic cell array 4 having a basic cell 3 made of a transistor or the like arranged in the x-axis direction in the wiring region 5. The configuration is arranged repeatedly in the y-axis direction with the gap between them. In order to obtain the desired electrical circuit characteristics, one or several adjacent basic cells 3 are connected to form a logic gate block such as a NAND gate or flip-flop that achieves the desired circuit function. Then, one LSI is formed by connecting these logic gate blocks according to the logic diagram. The wiring between these logic gate blocks is automated by the calculator.

2 shows an example of the basic cell 3 in a plan view. The basic cell 3 is formed to form a P ⁺ type region 6 serving as a source or a drain of a PMOS transistor, an N ⁺ type region 7 serving as a source or a drain of an NMOS transistor, and an N ⁺ type region 7 to form a N ⁺ type region. P-well region 11 formed on the type substrate, two polysilicon gate electrodes 8 shared by the P and NMOS transistors, Vcc power line 12 for supplying power to both transistors, GND power line 12, A contact hole 10 for connecting the P ⁺ , N ⁺ regions 6, 7 and the Al wiring (not shown), and a contact hole 9 for connecting the gate electrode 8 and the Al wiring. have.

3 shows the cross-sectional structure of the basic cell 3, the wiring region 5, and the structure of the wiring layer. The same thing as 2nd degree is shown with the code | symbol. Functional elements such as transistors are formed on one surface side of the N-type semiconductor substrate 20. The field oxide film 21 exists on one surface of the substrate 20 and has a film thickness of about 1 μm. A gate oxide film 31 is provided under the gate electrode 8 of the transistor, and has a film thickness of 500-1000 mW. An insulating film 22 is formed on the polysilicon wiring constituting the gate electrode 8, and a conductor, for example, Al, is the power supply wiring 12, 13 or Al, most of which is parallel to the X-axis direction in the longitudinal direction. First wirings of the wirings 25 and 26 are formed. The contact holes 9 and 10 are for connecting the polysilicon gate electrode 8 or the diffusion layers 6 and 7 to the first wiring. The second wirings 29 and 30 of Al are formed on the first wiring so that the insulating film 23 is again on most of them, and the longitudinal direction thereof is parallel to the y-axis direction. The contact hole 28 is for connecting the first wiring and the second wiring. Incidentally, although a plurality of contact holes are actually disposed, only a few are representatively shown in FIG. The uppermost layer has an insulating film 24 to protect the transistors and the wirings. In the normal master slice LSI, the desired LSI is obtained by changing the mask for the contact hole for connecting the first wiring, the second wiring and both. In addition, it is not necessary to arrange the wiring region 5, and the basic cells are arranged adjacent to each other with high density without disposing such wiring regions.

In order to increase the integration density of the master slice LSI, it is necessary to design the base cell 3 and the wiring area 5 in a small size. The former can be miniaturized to some extent by the miniaturization of CMOS, but the latter is limited in miniaturization since it is necessary to secure the number of wiring channels to depend on the number and gate count of the automatic wiring system DA (Design Automation). In addition, it is necessary to take a large wiring area in the basic cell so that the wiring pattern of an arbitrary logic gate block can be formed. Therefore, it is necessary to use not only the first wiring layer but also the second wiring layer for the internal wiring of the logic gate block for the purpose of miniaturization of the basic cell. The "logical gate block" refers to a circuit for achieving one circuit function, for example, as shown in FIG. The " basic cell " is a logic gate block formed by connecting some of the basic cells by wiring.

For example, a large logic gate block such as a conventional JK flip-flop (hereinafter referred to as JKFF) or a counter cannot design a wiring pattern of a logic gate block without using such a second wiring (protruded wiring layer). There are many. However, these protruding wirings reduce the empty channels of the second wirings, and there is a disadvantage in that the unwiring coefficient increases because the restriction on the automatic wiring by the calculator is increased. "Free channel" refers to a channel that can be wired in a computer's automatic wiring design.

4 shows a logic gate block 60 of a two-input NAND gate. A and B are input terminals of this NAN gate, and C is an output terminal. These input / output terminals have equipotential terminals A ', B', and C 'on opposite sides, respectively. FIG. 4 (b) shows an example of the wiring protruding in the logic gate block 60, and X denoted by TH is a contact hole for connecting the first wiring and the second wiring. ) Further, the solid line AL ₁ is the wiring, and the broken line AL2 of the first of Al shows the wiring of a second of Al. Next, the prior art will be described taking as an example a schematic diagram of this logic gate block.

FIG. 5 illustrates a combination of wiring patterns (by automatic wiring of a computer), for example, using the equipotential terminals A and A 'in the logic gate block of FIG. 4 (a). You can think of branches.

Fig. 5A: It is connected to the input terminal A by the second wiring AL2 in the upward direction of the ground.

Fig. 5B: In the downward direction of the ground, the second wiring AL2 is connected to the input terminal A and the input terminal A 'which is equipotential.

Fig. 5C: It is connected to the input terminal A by the first wiring AL1 in the upward direction of the ground.

FIG. 5D: Connects to the input terminals A and A 'by the first wiring AL1 in the upward direction and the downward direction of the ground.

Fig. 5f: It is connected to the input terminal A by the first wiring AL1 in the upward direction of the ground, and is connected to the input terminal A 'by the second wiring AL2 in the downward direction of the ground.

Fig. 5G: It is connected to the input terminal A by the second wiring AL2 in the upward direction of the ground, and is connected to the input terminal A 'by the first wiring AL1 in the downward direction of the ground.

Fig. 5h: It is connected to the input terminals A and A 'by the second wiring AL2 in the upward direction and the downward direction to the ground.

Since there is one protruding wiring 100 for forming the logic gate block 60 on the insulating film 23 as one of the second wirings, the second wiring cannot be disposed at the same position of the protruding wiring 100. Of course.

Therefore, when the computer performs the automatic design of the wiring, the place where the wiring 100 exists does not become a channel available for another wiring, that is, an empty channel.

Thus, there exists a fault which reduces the number of the free channel for the 2nd wiring AL2 used for the wiring with which presence of wiring 100 differs.

6 shows a specific conventional example having no equipotential terminal. 5 and the same reference numbers indicate the same and equivalent. As shown in Fig. 6 (a) to Fig. 6 (c), three types of patterns by automatic wiring to the input terminal A " can be considered.

Since the second wiring AL2 is provided with one wiring 100 protruding to form the logic gate block 60 again, the second wiring AL2 is more likely to use two shares of channels in the automatic wiring. As the number of channels for automatic wiring is lowered, there is a problem that the density of mounting possible is lowered.

An object of the present invention is to provide a semiconductor integrated circuit with high integration density by increasing the design freedom of automatic placement and automatic wiring DA by a calculator.

A feature of the present invention which achieves the above object is that a plurality of basic cells comprising at least a plurality of functional elements on one main surface are arranged in one direction to form a basic cell, and the plurality of basic cell arrays are arranged in a direction perpendicular to the basic cell array. The semiconductor chip formed by the parallel wiring, the at least 1st wiring and the 2nd wiring laminated | stacked on a semiconductor chip via the insulating film, and the at least 1 basic cell are formed by wiring by the 1st wiring and the 2nd wiring, A semiconductor integrated circuit device having a logic gate block for achieving a circuit function of the semiconductor device, wherein at least one of the second wirings for forming the logic gate block is present so that at least one input / output terminal of the logic gate block exists in its extension direction. To excrete.

The principle of the present invention will be described with reference to FIGS. 7 and 8. 7 is a view corresponding to FIG. 5, FIG. 8 is a view corresponding to FIG. 6, and the same reference numerals as those in FIG. 5 denote the same and equivalents.

7A to 7H show eight types of wiring patterns to the input terminals A and A 'of the logic gate block 60, respectively, and the logic gate block 60 differs from each other by these wirings (not shown). Is connected to.

The wiring patterns of FIGS. 7A to 7H correspond to the wiring patterns of FIGS. 5A to 5H, respectively, and the different wiring patterns protrude on the extension lines of the input terminals A and A ', that is, the second wiring 100. This is just what exists.

Since there exists the wiring 100 which protruded in each figure of FIG. 5, FIG. 6, the automatic design which arrange | positions another 2nd wiring in the same place was not possible conventionally. However, as shown in each of Figs. 7 and 8, the place 150 (the same place where the wiring 100 of Figs. 5 and 6 was present) becomes an empty channel, and the computer is different from this place. It can be designed to arrange wiring. In other words, the degree of freedom in designing a computer can be increased, and the degree of integration of circuits can be increased.

개 AL2를 사용할 가능성이 있다. 본 실시예의 경우에는 돌출된 배선(100)이 입력단자의 연장상에 있으므로, 1기본셀당의 AL2가 사용되는 개수는 1개뿐이다. 따라서, 기본셀이 50개 존재하고 있으면,

×50에 의해 31개 AL2의 채널을 절약할 수 있게 된다.For example, if 50 logic gate blocks as shown in Figs. 7A to 7H are arranged on one basic cell array 4 shown in Fig. 1, according to this embodiment, the second wiring AL2 You can save 31 channels. The reason is explained next. In the case of Fig. 5, the number of AL2 used for one basic cell is one of eight (A)-(H) (A) (B) (F) (G) of the input terminal other than one of the protruding wiring 100. Since we use AL2 for 5 of (H),

There is a possibility of using dog AL2. In the case of this embodiment, since the protruding wiring 100 extends on the input terminal, only one AL2 is used per basic cell. Therefore, if there are 50 basic cells,

By x50, 31 channels of AL2 can be saved.

In addition, it will be easily understood that the idea of the present invention can be applied to the other input terminals B, B 'and the output terminals C, C', which are not limited to the input terminals A and A '. .

8a to 8c show the principle of the present invention in the absence of an equipotential terminal.

8A to 8C show three types of wiring patterns to the input terminal A "of the logic gate block 60, respectively, and the logic gate block 60 is connected to other logic gate blocks not shown by these wirings.

개 AL2를 사용할 가능성이 있다. 본 실시예의 제 8 도의 경우에는 돌출된 배선(100)이 입력단자의 연장상에 있으므로, 1기본셀당의 AL2가 사용되는 개수는 1개뿐이다. 따라서, 기본셀이 50개 존재하고 있으면,

×50에 의해 16개 AL2의 채널을 절약할 수 있다.Referring to FIGS. 8A to 8C, the second wiring is assumed that 50 blocks exist in one basic cell array 4 shown in FIG. 1 compared with the conventional example shown in FIG. You can save 16 channels. The reason is explained next. In the case of Fig. 6, the number of AL2 used for one basic cell is one of three of (A) of three (A) (B) and (C) at the input terminal in addition to one of the protruding wiring 100. As I use it,

There is a possibility of using dog AL2. In the case of FIG. 8 of this embodiment, since the protruding wiring 100 is on the extension of the input terminal, only one AL2 is used per one basic cell. Therefore, if there are 50 basic cells,

16 channels can be saved by x50.

Next, the wiring pattern in the case where the four-input multiplexer as shown in FIG. 9 is used as the logic gate block is shown in FIG. 10 as the first embodiment of the present invention.

First, the four-input multiplexer in FIG. 9 will be described.

"1"레벨, S0-1=S0.2="0"레벨로 되므로, 3입력 AND게이트(102)만이 액티브로되어 신호 A0를 선택하며, 출력 B=A0(A0의 인버터신호)로 된다(AND게이트 103,104,105의 출력은 "0"레벨).The four input multiplexer of FIG. 9 is a four input NOR gate 101, a three input AND gate 102, 103, 104, 105, and inverters 106, 107, 108, ( 109). One of the input signals A0, A1, A2, and A3 is selected according to the logic levels of the address signals S0 and S1, and is transmitted as the output B. For example, when S0 = S1 = "0" level,

Since the level is "1", S0-1 = S0.2 = "0", only the three-input AND gate 102 is activated to select the signal A0, and the output B = A0 (the inverter signal of A0) ( The outputs of the AND gates 103, 104, 105 are at " 0 " level).

In FIG. 10, the basic cell 3 is a P ⁺ diffusion layer 6 constituting a source or a drain of a PMOS, an N ⁺ diffusion layer 7 constituting a source or a drain of an NMOS, and polysilicon common to both MOSs. A contact hole 9 for connecting the gate electrode 8, the first wiring AL1 indicated by the thick solid line and the polysilicon gate electrode 8, and the P ⁺ diffusion layer 6 and the N ⁺ diffusion layer 7 and the first The contact hole 10 for connecting the wiring AL1 is made of. (12) and (13) are Vcc and GND power supply lines respectively formed by the first wiring AL1. Reference numeral 50 denotes a contact hole for biasing the N-type substrate to Vcc, and 51 denotes a contact hole for biasing the P well region (not shown) to the GND potential. Broken lines 70, 71, 72, 73, 74, and 75 represent second wirings of Al. X represents the contact hole which connects a 1st wiring and a 2nd wiring. The base cells 3 are arranged in parallel in the x-axis direction at the pitch of BW (eight of them are shown in FIG. 10) to form the base cell array 4. Although not shown in the drawing, a plurality of the basic cell rows 4 are arranged in the y-axis direction through wiring areas at predetermined intervals. In addition, in FIG. 10, 9th and the same code | symbol show the same thing and an equivalent.

In FIG. 10, four basic multiplexers are formed by eight basic cells 3, which form one logical gate convex.

In this figure, the second wiring 70 for forming the four-input multiplexer is arranged such that an input terminal 300 into which the address signal SO of the four-input multiplexer is input in the extending direction is present. Similarly, the second wiring 73 has an input terminal 303 to which the input signal A1 'of the four input multiplexer is input in its extension direction, and the second wiring 75 has an input of the four input multiplexer in its extension direction. The input terminal 305 to which the signal A3 'is input is disposed to exist.

Therefore, in the present embodiment, when the input / output terminal of the four input multiplexer and the input / output terminal of the other logic gate block are automatically wired and connected by the second wiring (not shown), almost all the channels of the second wiring can be used. The problem that the channel of the second wiring (projected wiring) for forming the logic gate block cannot be used as in the conventional example can be solved.

Next, a second embodiment of the present invention is shown in FIG. The same thing as the 10th figure is shown with the same number and symbol. In Fig. 11, input / output terminals S0 (equal potential terminal is S0 '), A0 (copotential terminal is A0'), A1 (equal potential terminal is A1 '), A2 (equal potential terminal is A2'), A3 (equal potential terminal) A3 'is on the extension lines of the second wirings 70, 71, 73, 74, and 75 which are protruding wirings, respectively. In this embodiment, the pin position is changed so that the pin is on the extension line of the second wiring AL2 by running the boundary of the basic cell (the width of the basic cell is indicated by BL in FIG. 11) to the first wiring AL1. It also has the effect of simply changing the pin position, as long as it does not conflict with other signal pins.

According to each embodiment of the present invention, even if there is a protruding wiring of the second wiring AL2 in the logic gate block, the bin for the second wiring AL2 for DA is effectively provided by arranging the protruding wiring on the extension line of the input / output terminal. The drastic reduction of a channel can be suppressed. Therefore, the base cell size can be reduced by the protruding wiring of the second wiring AL2 and the integration density of the master slice LSI can be increased without increasing the burden on the DA system. In addition, since the chip size can be made small, the cost can be reduced.

In the above description, although the 1st wiring AL1 and the 2nd wiring AL2 were mentioned for convenience, this invention is not limited to this, For example, arbitrary layers of 3 or more multilayer wirings can be applied also in wiring. It is easy to think of it.

As described above, according to the present invention, it is possible to form a basic cell in a small size and to obtain a semiconductor integrated circuit device with a high density without disturbing the support of automatic placement and automatic wiring by a calculator.

Claims (8)

(a) a basic cell array in which a plurality of basic cells composed of a plurality of functional elements are arranged in a first direction on a main surface of a semiconductor chip, and a plurality of basic cell arrays are arranged in a second direction substantially perpendicular to the first direction; And (b) a first insulating film stacked on the semiconductor chip in which a plurality of the basic cell rows are arranged, and (c) the plurality of basic cells are connected to each other to achieve a desired circuit function. (1) a plurality of first wirings arranged in parallel on said first insulating film, (d) a plurality of first holes formed in said first insulating film for connecting said base cell and said first wiring, and (e) said first wiring A second insulating film laminated on the first wiring; (f) a plurality of second wirings arranged in parallel on the second insulating film so as to connect the first wirings so as to achieve the desired circuit function; and (g 1st above A semiconductor integrated circuit having a logic gate block composed of a plurality of second holes formed in the second insulating film for connecting the second wiring with the second wiring, wherein at least one second wiring of the plurality of second wirings is extended. And at least one terminal of an input terminal and an output terminal for the logic gate block in a direction. The semiconductor integrated circuit according to claim 1, wherein an equipotential terminal having the same potential as at least one of the input terminal and the output terminal exists in an extension direction of the second wiring. 2. The semiconductor integrated circuit according to claim 1, wherein the direction in which the second wiring is arranged is a second direction substantially perpendicular to the first direction. 3. The semiconductor integrated circuit according to claim 2, wherein the direction in which the second wiring is arranged is a second direction substantially perpendicular to the first direction. The semiconductor integrated circuit according to claim 1, wherein a wiring area is provided between said basic cells. The semiconductor integrated circuit according to claim 2, wherein a wiring area is provided between the basic cells. 2. The semiconductor integrated circuit according to claim 1, wherein a third insulating film is again disposed on said second wiring, and a plurality of third wirings are disposed thereon. 3. The semiconductor integrated circuit according to claim 2, wherein a third insulating film is again disposed on the second wiring, and a plurality of third wirings are disposed thereon.

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