KR900002490Y1 - Voltage circuit - Google Patents

Voltage circuit Download PDF

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Publication number
KR900002490Y1
KR900002490Y1 KR2019870006273U KR870006273U KR900002490Y1 KR 900002490 Y1 KR900002490 Y1 KR 900002490Y1 KR 2019870006273 U KR2019870006273 U KR 2019870006273U KR 870006273 U KR870006273 U KR 870006273U KR 900002490 Y1 KR900002490 Y1 KR 900002490Y1
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operational amplifier
resistor
voltage
output
diode
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KR2019870006273U
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KR880020291U (en
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박상규
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주식회사광진전자
강선대
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/461—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using an operational amplifier as final control device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음.No content.

Description

정전압 유지회로Constant voltage holding circuit

도면은 본 고안의 회로도The drawing is a circuit diagram of the present invention

*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

R1~R4: 저항 D1~D3: 다아오드R 1 to R 4 : Resistance D 1 to D 3 : Diode

ZD1, ZD2: 제너다이오드 C1~C5: 콘덴서ZD 1 , ZD 2 : Zener Diodes C 1 to C 5 : Condenser

TR1~TR3: 트랜지스터 VR1~VR4: 볼륨TR 1 to TR 3 : Transistor VR 1 to VR 4 : Volume

OP1~OP4: 연산증폭기 B1: 출력전압검출회로OP 1 to OP 4 : Operational Amplifier B 1 : Output Voltage Detection Circuit

B2: 톱니파발진기 B3: 비교기B 2 : Sawtooth Oscillator B 3 : Comparator

본 고안은 싸이리스터를구동시키는 정전압 유지회로에 관한 것으로, A·C입력 전압의 변동 여하에 관계없이 출력전압을 일정하게 유지시키도록 펄스폭(Trigger pulse wide)을 자동으로 조절 할 수 있도록 함에 그 주안점을 둔 것이다.The present invention relates to a constant voltage holding circuit for driving a thyristor, and is capable of automatically adjusting the pulse width to keep the output voltage constant regardless of the variation of the A / C input voltage. The focus is on.

종래에는 이와같은 고안이 안출되지 않았음, 따라서 입력전압의 변동에 따라 출력전압의 폭도 임의대로 변동함을서 각종 전기기기의 수명이 단축되는 등 이로 파생되는 문제점이 많은 실정이다.In the related art, such a design has not been devised, and thus, there are many problems caused by shortening the lifespan of various electric devices by varying the width of the output voltage arbitrarily according to the variation of the input voltage.

궤환(Feed Back)된 파형을 전파정한 다음, 피크 전압 검출 회로(peak voltage value defector circuit)를 거쳐 출력전압 검출 회로(B1)에 입력되도록 연결함에 있어, 출력전압 검출회로(B1)를구성하는 연산증폭기(op1)의-단자에는 저항(R1)을 연결하고, +단자에는 볼륨(VR1)에 인가된 저항(R2)을 연결하며, 또한 -단자와 다이오드(D1)사이에는 콘덴서(C1)(C2)와 저항(R3)을 각각 접속하고, 연산증폭기(op1)의 출력단자는 제너다이오드(ZD1), 다이오드(D2), 저항(R4)의 병렬회로에 연결하여, 볼륨(VR2)은 저항(R5)을 통하여 연산증폭(op2)의 +단자에 인가하고, -단자는 출력단자와 연결된 저항(R6)사이에 접속한다.The output voltage detection circuit B 1 is configured by connecting the fed back waveform to be inputted to the output voltage detection circuit B 1 through a peak voltage value defector circuit. The resistor (R 1 ) is connected to the-terminal of the operational amplifier (op 1 ), and the resistor (R 2 ) applied to the volume (VR 1 ) is connected to the + terminal, and between the terminal and the diode (D 1 ). The capacitor C 1 (C 2 ) and the resistor R 3 are respectively connected to each other, and the output terminal of the operational amplifier op 1 is a parallel circuit of a zener diode (ZD 1 ), a diode (D 2 ), and a resistor (R4). In connection with, the volume VR 2 is applied to the + terminal of the operational amplifier op 2 via the resistor R 5 , and the-terminal is connected between the output terminal and the resistor R 6 connected.

한편, 톱니파발진기(B2)를 구성하는 트랜지스터(TR1), (TR2), (TR3), 및 저항(R7), (R8), (R9), (R10)과 콘덴서(C3)에서 진폭이 큰 펄스를 연산증폭기(op3)의 +에 인가하고, 볼륨(VR3)과 저항(R11), (R12)및 다이오드(D3), (D4)에 의해 진폭이 적은 펄스는 연산증폭기(op3)의 -에 인가하며, 제너다이오드(ZD1), 콘덴서(C)를 각각 이에 접속하여서 된것을, 출력전압 검출회로(B)와 톱니파 발진기(B2)를 각각 비교기(B3)를구성하는 연산증폭기(op4)의 -와 +에 각각 연결하여서 구성된 것이다.On the other hand, the transistors TR 1 , TR 2 , TR 3 , and resistors R 7 , R 8 , R 9 , R 10 , and the capacitor constituting the sawtooth oscillator B2 ( In C 3 ), a pulse having a large amplitude is applied to the + of the operational amplifier op 3 and the volume VR 3 and the resistances R 11 , R 12 , and the diodes D 3 and D 4 are applied. A pulse of low amplitude is applied to-of the operational amplifier op 3 , and is connected by connecting the zener diode ZD 1 and the capacitor C to the output voltage detection circuit B and the sawtooth wave oscillator B 2 . Are connected to the-and + of the operational amplifier (op 4 ) constituting the comparator (B 3 ), respectively.

이와같이된, 본 고안의 작용효과를 상세히 설명하면 다음과 같다.As described above, the effects of the present invention will be described in detail.

출력전압검출회로(B1)의 볼륨(VR1)에 걸리는 전압(DㆍC Refference Voltage)이 연산증폭기(op1)의 +입력단자에 인가되고, 피크전압검출회로의 출력이 연산증폭기(op1)의 -입력단자에 인가되여, 이 입력된 전압을 연산증폭기(op1)에서 +와 -의 입력 차이 전압을 저항(R1), (R2)을 통해 invecter(-)로 증폭한다.The voltage D · C Refference Voltage applied to the volume VR 1 of the output voltage detection circuit B 1 is applied to the + input terminal of the operational amplifier op 1 , and the output of the peak voltage detection circuit is supplied to the operational amplifier op. It is applied to the input terminal of 1 ), and amplifies this input voltage to the invecter (-) through the resistors R 1 and R 2 in the operational amplifier op 1 .

이때 콘덴서(C1),(C2)는 전해콘덴서의 압출력 평활용으로 사용되며, 연산증폭기(op1)의 출력단자에 병렬로 연결된 제너다이오드(ZD1)다이오드(D2), 저항(R4)은 Vcc에 공급되는 전압대 op1의 출력과의 차이나는 전압을 다이오드(D1) 를 통하여 by pass시키며, 볼륨(VR2)에 인가되는 전압을 저항(R5)을 통하여 연산증폭기(op2)의 +단자에 인가하게 된다.The capacitor (C 1), (C 2 ) is delivered and used by utilizing pressure output spur of the capacitor, the operational amplifier zener diode (ZD 1) a diode (D 2) connected in parallel to the output terminal of the (op 1), resistance ( R 4 ) passes through the diode D 1 a voltage that is different from the output of the voltage band op 1 supplied to Vcc through the diode D 1 , and the voltage applied to the volume VR 2 through the operational amplifier R 5 . It is applied to the + terminal of (op 2 ).

그러므로, 연산증폭기(op1)의 출력에 따란 연산증폭기(op2)의 입력 전압을 변화하고 또한, 연산증폭기(op2)의 출력은 비교기(B3)에 입력이 된다.Therefore, the input voltage of the operational amplifier op 2 is changed in accordance with the output of the operational amplifier op 1 , and the output of the operational amplifier op 2 is input to the comparator B 3 .

한편, 트랜지스터(TR1)의 베이스에 Bias signal가 없을때 트랜지스터(TR2)는 ON되고 트랜지스터(TR3)는 OFF되며, 콘덴서(C3)에는 전압이 충전되고, 콘덴서(C4)는 볼륨(VR3)과 저항(R11)을 통하여 충전이 되기 시작한다.On the other hand, when there is no bias signal at the base of the transistor TR 1 , the transistor TR 2 is turned on, the transistor TR 3 is turned off, the capacitor C 3 is charged with a voltage, and the capacitor C 4 is turned on. Charging begins via (VR 3 ) and resistor (R 11 ).

이때, 트랜지스터(TR1)의 베이스에 Bias signal가 인가되면, 트랜지스터(TR1)은 ON되고, Vcc전압이 저항(R7)과 트랜지스터(TR1)를 통하여 by pass가 되고, 이때 콘덴서(C3)에 충전되었던 전압이 방전함으로서 연산증폭기(op3)의 +입력단에 인가된다.At this time, when the base of the transistor (TR 1) Bias signal is applied, a transistor (TR 1) is ON, the Vcc voltage, and the by pass through the resistor (R 7) and a transistor (TR 1), wherein the capacitor (C The voltage charged in 3 ) is applied to the + input terminal of the operational amplifier op 3 by discharging.

그리고, 트랜지스터(TR1)가 ON일때, 콘덴서(C4)에 충전된 저압이 방전되어 저항(R12)과 다이오드(D3)에 인가되는 전압이 역시 pulse형태로 연산증폭기(op3)의 -입력단에 인가되여, 여기서 트랜지스터(TR1)는 두펄스의 위상을 맞추어 스위치를 사용한다.When the transistor TR 1 is turned on, the low voltage charged in the capacitor C 4 is discharged so that the voltage applied to the resistor R 12 and the diode D 3 is also in the form of a pulse of the operational amplifier op 3 . Applied to the input stage, where transistor TR 1 uses a switch to match the phase of the two pulses.

그리고, 볼륨(VR3)의 조정으로 콘덴서(C4)양단에 걸리는 전압을 조정할 수있으므로, 결과적으로 연산증폭기(op3)의 출력에 나타날 톱니파의 경사각을 조정할 수 있다.Since the voltage across the capacitor C 4 can be adjusted by adjusting the volume VR 3 , the inclination angle of the sawtooth wave appearing at the output of the operational amplifier op 3 can be adjusted.

이것은 연산증폭기(op4)의 출력펄스를 maximun pulse wide를 결정할 수있다. 한편, 연산증폭기(op3)의 출력은 저항(R13)을 통하여 볼륨(VR4)과 저항(R14)을 통하여 Vcc의 D. C성분과 합쳐서 D. C성분을 포함한 톱니파가 연산증폭기(op4)의 +입력에 인가되며, 이때 D. C성분의 전압을 볼륨(VR4)의 조정으로 결정지어지며, 저항(R14)의 최소치로 만들기위한 저항이며, 볼륨(VR4)의 조정으로 결정된 D. C성분을 연산증폭기(op4)의 출력 즉, minimun pulse wide를 결정 할 수 있다.This can determine the maximum pulse wide for the output pulse of the op amp op 4 . On the other hand, an operational amplifier (op 3) the output of which a sawtooth wave, including D. C ingredients together and Vcc of the D. C components by the volume (VR 4) and resistance (R 14) via the resistor (R 13) operational amplifier ( op 4) it is applied to the + input, this time becomes built D. determining the voltage of the C component in the adjustment of the volume (VR 4), the resistance to make the minimum value of the resistance (R 14), adjust the volume (VR 4) Based on the D. C component determined by, the output of the operational amplifier (op 4 ), that is, the minimun pulse wide can be determined.

이 모든 회로의 동작으로 연산증폭기(op4)의 양입력에 인가되는 전압을 comparator(op4)로 동작하는 연산증폭기(op4)의 출력측에 해당 pulse가 나오고, 이 펄스 출력은 Thyristor dirve circuit로 보내오 출력전압을 일정하게 유지하게 된다.By the operation of all these circuits, the voltage applied to both inputs of the operational amplifier (op4) is output to the output side of the operational amplifier (op4) operated by the comparator (op4), and this pulse output is sent to the thyristor dirve circuit. Will be kept constant.

Claims (1)

연산증폭기(op1)의 -단자와 +단자에 저항(R1)과 볼륨(VR1)에 인가된 저항(R2)에 인가된 저항(R2) 및 콘덴서(C1), (C2), 저항(R3)을 각각 연결하고, 출력단자는 제어다오드(ZD1), 다이오드(D2), 저항(R3)의 병렬회로에 연결하며, 연산증폭기(op2)의 +단자와 -단자에는 볼륨(VR2)과 저항(R6)을 각각 연결하여 구성한 출력전압검출회로(B1)와, 트랜지스터(TR1)~(TR3) 및 저항(R7)~(R10)과 콘덴서(C3)에서 진폭이 큰 펄스를 연산증폭기(op3)의 +에, 볼륨(VR3)과 저항(R11) 및 다이오드(D3), (D4)에 의해 진폭이 적은 펄스는 -에 각각 인가하고, 제너다이오드(ZD2), 콘덴서(C5)를 접속하여 구성한 톱니파발진기(B2)를 비교기(B3)를 구성하는 연산증폭기(OP2)의 -와 +에 각각 연견하여 구성함에 특징으로 하는 정전압 유지 회로.Operational amplifiers (op 1) - a resistor (R 2) and a condenser applied to the resistance (R 2) applied to the resistor (R 1) and volume (VR 1) to the terminal and the + terminals (C 1), (C 2 ) And the resistor (R 3 ), respectively, and the output terminal is connected to the parallel circuit of the control diode (ZD 1 ), diode (D 2 ) and resistor (R 3 ), and the + terminal of the operational amplifier (op 2 ) An output voltage detection circuit (B 1 ), transistors (TR 1 ) to (TR 3 ) and resistors (R 7 ) to (R 10 ) configured by connecting a volume (VR 2 ) and a resistor (R 6 ) to the terminals, respectively. In the condenser (C 3 ), a pulse with a large amplitude is added to the + of the operational amplifier (op 3 ), and the pulse has a small amplitude by the volume (VR 3 ), the resistor (R 11 ), and the diode (D 3 ), (D 4 ). Are respectively applied to-, and the sawtooth oscillator B 2 formed by connecting the zener diode (ZD 2 ) and the capacitor (C 5 ) to the-and + of the operational amplifier (OP 2 ) constituting the comparator (B 3 ), respectively. A constant voltage holding circuit, characterized in that configured in connection.
KR2019870006273U 1987-04-27 1987-04-27 Voltage circuit KR900002490Y1 (en)

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Application Number Priority Date Filing Date Title
KR2019870006273U KR900002490Y1 (en) 1987-04-27 1987-04-27 Voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019870006273U KR900002490Y1 (en) 1987-04-27 1987-04-27 Voltage circuit

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KR880020291U KR880020291U (en) 1988-11-30
KR900002490Y1 true KR900002490Y1 (en) 1990-03-30

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KR2019870006273U KR900002490Y1 (en) 1987-04-27 1987-04-27 Voltage circuit

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