KR890015134A - Extension system - Google Patents

Extension system Download PDF

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Publication number
KR890015134A
KR890015134A KR1019890004053A KR890004053A KR890015134A KR 890015134 A KR890015134 A KR 890015134A KR 1019890004053 A KR1019890004053 A KR 1019890004053A KR 890004053 A KR890004053 A KR 890004053A KR 890015134 A KR890015134 A KR 890015134A
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KR
South Korea
Prior art keywords
address
semiconductor chip
expansion
lsi semiconductor
cache
Prior art date
Application number
KR1019890004053A
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Korean (ko)
Other versions
KR920001811B1 (en
Inventor
가쥬유키 사토
Original Assignee
아오이 죠이치
가부시기가이샤 도시바
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Application filed by 아오이 죠이치, 가부시기가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR890015134A publication Critical patent/KR890015134A/en
Application granted granted Critical
Publication of KR920001811B1 publication Critical patent/KR920001811B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

내용 없음.No content.

Description

확장 시스템Extension system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 확장 시스템의 구성을 나타내는 블록도.2 is a block diagram showing the configuration of the expansion system of the present invention.

제3도는, 제2도의 실시예에 있어서, 각 캐쉬 LSI에 설치된 확장핀의 레벨 할당을 나타내는 테이블.FIG. 3 is a table showing the level assignment of expansion pins provided in each cache LSI in the embodiment of FIG.

제5도는 본 발명의 확장 시스템에 있어서 판별회로의 상세 회로도.5 is a detailed circuit diagram of a discrimination circuit in the expansion system of the present invention.

Claims (8)

어드레스를 제공하는 수단과; 상기 어드레스 제공수단에 접속되어, 소정의 레벨로 세트되는 적어도 하나의 확장핀과, 어드레스데이타 및 확장핀 레벨의 논리연산을 실행하는 수단과, 상기 논리연산 실행수단에 따라 자기 LSI 반도체 칩을 선택 결정하는 수단을 각각이 가진 복수의 LSI 반도체칩을 포함하는 것을 특징으로 하는 확장 시스템.Means for providing an address; At least one expansion pin set to a predetermined level, connected to the address providing means, means for executing logical operations at address data and extended pin levels, and selecting and determining a magnetic LSI semiconductor chip according to the logic operation executing means; And a plurality of LSI semiconductor chips each having a means to do so. 제1항에 있어서, 상기 확장핀을 접지 레벨 또는 전원 전압 레벨중 어느하나의 레벨로 세트되는 것을 특징으로 하는 확장 시스템.2. The expansion system of claim 1, wherein the expansion pin is set to one of a ground level and a power supply voltage level. 제1항에 있어서, 상기 복수의 반도체 칩 각각은 캐쉬 LSI반도체 칩인 것을 특징으로 하는 확장 시스템.The expansion system of claim 1, wherein each of the plurality of semiconductor chips is a cache LSI semiconductor chip. 제3항에 있어서, 상기 캐쉬 LSI 반도체 칩에 대한 캐쉬 디렉토리는 그룹화된 블록을 지정하기 위한 세트 어드레스 필드를 포함하고, 상기 어드레스 공급수단은 세트 어드레스를 제공하는 것을 특징으로 하는 확장시스템.4. The expansion system of claim 3, wherein the cache directory for the cache LSI semiconductor chip includes a set address field for specifying a grouped block, and wherein the address supply means provides a set address. 어드레스 데이타를 출력하기 위한 마이크로 프로세서와 ; 어드레스 데이타를 전송하기 위한 버스와 ; 상기 버스를 통해 상기 마이크로프로세서와 접속되며, 소정의 레벨로 세트되는 적어도 하나의 확장핀과 어드레스 데이타 및 확장된 레벨의 논리 연산을 실행하는 수단과, 상기 논리연산 실행수단에 따라 자기 LSI 반도체칩을 결정하는 수단을 각각이 가진 복수의 LSI 반도체 칩을 포함하는 것을 특징으로 하는 확장 시스템.A microprocessor for outputting address data; A bus for transferring address data; Means for executing at least one expansion pin and address data and an extended level logic operation connected to the microprocessor through the bus, and a magnetic LSI semiconductor chip according to the logic operation execution means. And a plurality of LSI semiconductor chips each having a means for determining. 제5항에 있어서, 상기 확장핀은 접지레벨 또는 전원 전압레벨중 어느 하나의 레벨로 세트되는 것을 특징으로 하는 확장 시스템.6. The expansion system of claim 5, wherein the expansion pin is set to one of a ground level and a power supply voltage level. 제5항에 있어서, 상기 복수의 반도체 칩 각각은 캐쉬 LSI 반도체 칩인 것을 특징으로 하는 확장 시스템.6. The expansion system of claim 5 wherein each of the plurality of semiconductor chips is a cache LSI semiconductor chip. 제7항에 있어서, 상기 캐쉬 LSI 반도체 칩에 대한 캐쉬 디렉토리는 그룹화된 블록을 지정하기 위한 세트 어드레스를 포함하고, 상기 어드레스 공급수단은 세트 어드레스를 제공하는 것을 특징으로 하는 확장 시스템.8. The expansion system of claim 7, wherein the cache directory for the cache LSI semiconductor chip includes a set address for designating a grouped block, and wherein the address supply means provides a set address. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR8904053A 1988-03-30 1989-03-30 Expansion system KR920001811B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-76939 1988-03-30
JP63076939A JPH01251386A (en) 1988-03-30 1988-03-30 System extending system

Publications (2)

Publication Number Publication Date
KR890015134A true KR890015134A (en) 1989-10-28
KR920001811B1 KR920001811B1 (en) 1992-03-03

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Application Number Title Priority Date Filing Date
KR8904053A KR920001811B1 (en) 1988-03-30 1989-03-30 Expansion system

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JP (1) JPH01251386A (en)
KR (1) KR920001811B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9612970B2 (en) * 2014-07-17 2017-04-04 Qualcomm Incorporated Method and apparatus for flexible cache partitioning by sets and ways into component caches

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Publication number Publication date
JPH01251386A (en) 1989-10-06
KR920001811B1 (en) 1992-03-03

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